mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-29 05:18:51 +09:00
![Simon Glass](/assets/img/avatar_default.png)
This changes the number 15 as used in boot_stage_progress() to use the new name provided for it. This is a separate patch because it touches so many files. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Mike Frysinger <vapier@gentoo.org>
491 lines
12 KiB
C
491 lines
12 KiB
C
/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2004
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* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
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*
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* (C) Copyright 2010
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* Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc5xxx.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <libfdt.h>
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#include <netdev.h>
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#include <led-display.h>
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#include <linux/err.h>
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#include "mt46v32m16.h"
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#ifndef CONFIG_SYS_RAMBOOT
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static void sdram_start (int hi_addr)
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{
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long hi_addr_bit = hi_addr ? 0x01000000 : 0;
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long control = SDRAM_CONTROL | hi_addr_bit;
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/* unlock mode register */
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
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__asm__ volatile ("sync");
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/* precharge all banks */
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
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__asm__ volatile ("sync");
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#if SDRAM_DDR
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/* set mode register: extended mode */
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out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
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__asm__ volatile ("sync");
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/* set mode register: reset DLL */
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out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
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__asm__ volatile ("sync");
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#endif
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/* precharge all banks */
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
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__asm__ volatile ("sync");
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/* auto refresh */
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
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__asm__ volatile ("sync");
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/* set mode register */
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out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
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__asm__ volatile ("sync");
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/* normal operation */
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out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
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__asm__ volatile ("sync");
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}
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#endif
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/*
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* ATTENTION: Although partially referenced initdram does NOT make real use
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* use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
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* is something else than 0x00000000.
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*/
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phys_size_t initdram (int board_type)
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{
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ulong dramsize = 0;
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uint svr, pvr;
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#ifndef CONFIG_SYS_RAMBOOT
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ulong test1, test2;
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/* setup SDRAM chip selects */
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out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
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out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
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__asm__ volatile ("sync");
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/* setup config registers */
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out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
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out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
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__asm__ volatile ("sync");
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#if SDRAM_DDR
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/* set tap delay */
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out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
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__asm__ volatile ("sync");
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#endif
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/* find RAM size using SDRAM CS0 only */
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sdram_start(0);
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test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
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sdram_start(1);
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test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
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if (test1 > test2) {
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sdram_start(0);
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dramsize = test1;
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} else {
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dramsize = test2;
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}
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/* memory smaller than 1MB is impossible */
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if (dramsize < (1 << 20)) {
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dramsize = 0;
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}
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/* set SDRAM CS0 size according to the amount of RAM found */
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if (dramsize > 0) {
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out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
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0x13 + __builtin_ffs(dramsize >> 20) - 1);
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} else {
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out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
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}
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#else /* CONFIG_SYS_RAMBOOT */
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/* retrieve size of memory connected to SDRAM CS0 */
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dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
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if (dramsize >= 0x13) {
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dramsize = (1 << (dramsize - 0x13)) << 20;
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} else {
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dramsize = 0;
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}
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#endif /* CONFIG_SYS_RAMBOOT */
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/*
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* On MPC5200B we need to set the special configuration delay in the
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* DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
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* Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
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*
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* "The SDelay should be written to a value of 0x00000004. It is
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* required to account for changes caused by normal wafer processing
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* parameters."
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*/
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svr = get_svr();
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pvr = get_pvr();
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if ((SVR_MJREV(svr) >= 2) &&
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(PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
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out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
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__asm__ volatile ("sync");
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}
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return dramsize;
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}
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int checkboard (void)
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{
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puts ("Board: A4M072\n");
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return 0;
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}
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#ifdef CONFIG_PCI
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static struct pci_controller hose;
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extern void pci_mpc5xxx_init(struct pci_controller *);
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void pci_init_board(void)
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{
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pci_mpc5xxx_init(&hose);
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}
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#endif
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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void
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ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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}
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#endif
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int board_eth_init(bd_t *bis)
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{
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int rv, num_if = 0;
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/* Initialize TSECs first */
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if ((rv = cpu_eth_init(bis)) >= 0)
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num_if += rv;
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else
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printf("ERROR: failed to initialize FEC.\n");
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if ((rv = pci_eth_init(bis)) >= 0)
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num_if += rv;
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else
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printf("ERROR: failed to initialize PCI Ethernet.\n");
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return num_if;
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}
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/*
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* Miscellaneous late-boot configurations
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*
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* Initialize EEPROM write-protect GPIO pin.
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*/
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int misc_init_r(void)
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{
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#if defined(CONFIG_SYS_EEPROM_WREN)
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/* Enable GPIO pin */
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setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP);
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/* Set direction, output */
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setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP);
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/* De-assert write enable */
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setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
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#endif
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return 0;
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}
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#if defined(CONFIG_SYS_EEPROM_WREN)
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/* Input: <dev_addr> I2C address of EEPROM device to enable.
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* <state> -1: deliver current state
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* 0: disable write
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* 1: enable write
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* Returns: -1: wrong device address
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* 0: dis-/en- able done
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* 0/1: current state if <state> was -1.
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*/
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int eeprom_write_enable (unsigned dev_addr, int state)
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{
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if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
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return -1;
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} else {
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switch (state) {
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case 1:
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/* Enable write access */
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clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
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state = 0;
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break;
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case 0:
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/* Disable write access */
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setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP);
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state = 0;
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break;
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default:
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/* Read current status back. */
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state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) &
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CONFIG_SYS_EEPROM_WP));
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break;
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}
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}
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return state;
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}
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#endif
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#ifdef CONFIG_CMD_DISPLAY
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#define DISPLAY_BUF_SIZE 2
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static u8 display_buf[DISPLAY_BUF_SIZE];
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static u8 display_putc_pos;
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static u8 display_out_pos;
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void display_set(int cmd) {
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if (cmd & DISPLAY_CLEAR) {
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display_buf[0] = display_buf[1] = 0;
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}
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if (cmd & DISPLAY_HOME) {
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display_putc_pos = 0;
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}
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}
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#define SEG_A (1<<0)
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#define SEG_B (1<<1)
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#define SEG_C (1<<2)
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#define SEG_D (1<<3)
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#define SEG_E (1<<4)
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#define SEG_F (1<<5)
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#define SEG_G (1<<6)
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#define SEG_P (1<<7)
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#define SEG__ 0
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/*
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* +- A -+
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* | |
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* F B
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* | |
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* +- G -+
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* | |
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* E C
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* | |
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* +- D -+ P
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*
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* 0..9 index 0..9
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* A..Z index 10..35
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* - index 36
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* _ index 37
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* . index 38
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*/
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#define SYMBOL_DASH (36)
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#define SYMBOL_UNDERLINE (37)
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#define SYMBOL_DOT (38)
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static u8 display_char2seg7_tbl[]=
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{
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SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* 0 */
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SEG_B | SEG_C, /* 1 */
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SEG_A | SEG_B | SEG_D | SEG_E | SEG_G, /* 2 */
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SEG_A | SEG_B | SEG_C | SEG_D | SEG_G, /* 3 */
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SEG_B | SEG_C | SEG_F | SEG_G, /* 4 */
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SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* 5 */
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SEG_A | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 6 */
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SEG_A | SEG_B | SEG_C, /* 7 */
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SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 8 */
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SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* 9 */
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SEG_A | SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* A */
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SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* b */
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SEG_A | SEG_D | SEG_E | SEG_F, /* C */
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SEG_B | SEG_C | SEG_D | SEG_E | SEG_G, /* d */
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SEG_A | SEG_D | SEG_E | SEG_F | SEG_G, /* E */
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SEG_A | SEG_E | SEG_F | SEG_G, /* F */
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0, /* g - not displayed */
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SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* H */
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SEG_B | SEG_C, /* I */
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0, /* J - not displayed */
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0, /* K - not displayed */
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SEG_D | SEG_E | SEG_F, /* L */
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0, /* m - not displayed */
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0, /* n - not displayed */
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SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* O */
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SEG_A | SEG_B | SEG_E | SEG_F | SEG_G, /* P */
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0, /* q - not displayed */
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0, /* r - not displayed */
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SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* S */
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SEG_D | SEG_E | SEG_F | SEG_G, /* t */
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SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* U */
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0, /* V - not displayed */
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0, /* w - not displayed */
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0, /* X - not displayed */
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SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* Y */
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0, /* Z - not displayed */
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SEG_G, /* - */
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SEG_D, /* _ */
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SEG_P /* . */
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};
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/* Convert char to the LED segments representation */
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static u8 display_char2seg7(char c)
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{
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u8 val = 0;
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if (c >= '0' && c <= '9')
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c -= '0';
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else if (c >= 'a' && c <= 'z')
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c -= 'a' - 10;
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else if (c >= 'A' && c <= 'Z')
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c -= 'A' - 10;
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else if (c == '-')
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c = SYMBOL_DASH;
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else if (c == '_')
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c = SYMBOL_UNDERLINE;
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else if (c == '.')
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c = SYMBOL_DOT;
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else
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c = ' '; /* display unsupported symbols as space */
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if (c != ' ')
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val = display_char2seg7_tbl[(int)c];
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return val;
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}
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int display_putc(char c)
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{
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if (display_putc_pos >= DISPLAY_BUF_SIZE)
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return -1;
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display_buf[display_putc_pos++] = display_char2seg7(c);
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/* one-symbol message should be steady */
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if (display_putc_pos == 1)
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display_buf[display_putc_pos] = display_char2seg7(c);
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return c;
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}
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/*
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* Flush current symbol to the LED display hardware
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*/
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static inline void display_flush(void)
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{
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u32 val = display_buf[display_out_pos];
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val |= (val << 8) | (val << 16) | (val << 24);
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out_be32((void *)CONFIG_SYS_DISP_CHR_RAM, val);
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}
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/*
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* Output contents of the software display buffer to the LED display every 0.5s
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*/
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void board_show_activity(ulong timestamp)
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{
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static ulong last;
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static u8 once;
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if (!once || (timestamp - last >= (CONFIG_SYS_HZ / 2))) {
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display_flush();
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display_out_pos ^= 1;
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last = timestamp;
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once = 1;
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}
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}
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/*
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* Empty fake function
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*/
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void show_activity(int arg)
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{
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}
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#endif
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#if defined (CONFIG_SHOW_BOOT_PROGRESS)
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static int a4m072_status2code(int status, char *buf)
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{
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char c = 0;
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if (((status > 0) && (status <= 8)) ||
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((status >= 100) && (status <= 108)) ||
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((status < 0) && (status >= -9)) ||
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(status == -100) || (status == -101) ||
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((status <= -103) && (status >= -113))) {
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c = '5';
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} else if (((status >= 9) && (status <= 14)) ||
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((status >= 120) && (status <= 123)) ||
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((status >= 125) && (status <= 129)) ||
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((status >= -13) && (status <= -10)) ||
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(status == -120) || (status == -122) ||
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((status <= -124) && (status >= -127)) ||
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(status == -129)) {
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c = '8';
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} else if (status == 15) {
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c = '9';
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} else if ((status <= -30) && (status >= -32)) {
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c = 'A';
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} else if (((status <= -35) && (status >= -40)) ||
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((status <= -42) && (status >= -51)) ||
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((status <= -53) && (status >= -58)) ||
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(status == -64) ||
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((status <= -80) && (status >= -83)) ||
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(status == -130) || (status == -140) ||
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(status == -150)) {
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c = 'B';
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}
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if (c == 0)
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return -EINVAL;
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buf[0] = (status < 0) ? '-' : c;
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buf[1] = c;
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return 0;
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}
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void show_boot_progress(int status)
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{
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char buf[2];
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if (a4m072_status2code(status, buf) < 0)
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return;
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display_putc(buf[0]);
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display_putc(buf[1]);
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display_set(DISPLAY_HOME);
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display_out_pos = 0; /* reset output position */
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/* we want to flush status 15 now */
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if (status == BOOTSTAGE_ID_RUN_OS)
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display_flush();
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}
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#endif
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