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af523a0d56
u-boot-brain/arch/arm/include/asm/arch-fsl-layerscape
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Mingkai Hu af523a0d56 pci/layerscape: add support for LS1043A PCIe LUT register access 
The endian and base address of PEX LUT register region is different
between Chassis 2 and Chassis 3, so move the base address definition
to chassis specific header file and add pex_lut_* functions to access
LUT register.

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
2015-11-30 09:11:10 -08:00
..
clock.h armv8/fsl_lsch3: Change arch to fsl-layerscape 2015-10-29 10:34:00 -07:00
config.h pci/layerscape: add support for LS1043A PCIe LUT register access 2015-11-30 09:11:10 -08:00
cpu.h armv8: ls2085a: Add support of LS2085A SoC 2015-11-30 09:10:47 -08:00
fdt.h armv8/fsl_lsch3: Change arch to fsl-layerscape 2015-10-29 10:34:00 -07:00
fsl_serdes.h armv8: ls2085a: Add support of LS2085A SoC 2015-11-30 09:10:47 -08:00
immap_lsch2.h pci/layerscape: add support for LS1043A PCIe LUT register access 2015-11-30 09:11:10 -08:00
immap_lsch3.h pci/layerscape: add support for LS1043A PCIe LUT register access 2015-11-30 09:11:10 -08:00
imx-regs.h armv8/fsl_lsch3: Change arch to fsl-layerscape 2015-10-29 10:34:00 -07:00
ls2080a_stream_id.h armv8: LS2080A: Rename LS2085A to reflect LS2080A 2015-11-30 08:53:04 -08:00
mmu.h armv8/fsl_lsch3: Change arch to fsl-layerscape 2015-10-29 10:34:00 -07:00
mp.h armv8/fsl_lsch3: Change arch to fsl-layerscape 2015-10-29 10:34:00 -07:00
ns_access.h armv8/fsl_lsch2: Add fsl_lsch2 SoC 2015-10-29 10:34:00 -07:00
soc.h pci/layerscape: add support for LS1043A PCIe LUT register access 2015-11-30 09:11:10 -08:00
speed.h armv8/fsl_lsch3: Change arch to fsl-layerscape 2015-10-29 10:34:00 -07:00