mirror of
https://github.com/brain-hackers/u-boot-brain
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aef59e5cc4
This updates supports_extension() implementation to use the desc string from the cpu driver whenever possible, which avoids the reading of misa CSR for S-mode U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
71 lines
1.5 KiB
C
71 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <cpu.h>
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#include <dm.h>
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#include <log.h>
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#include <asm/csr.h>
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#include <dm/uclass-internal.h>
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/*
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* prior_stage_fdt_address must be stored in the data section since it is used
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* before the bss section is available.
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*/
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phys_addr_t prior_stage_fdt_address __attribute__((section(".data")));
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static inline bool supports_extension(char ext)
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{
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#ifdef CONFIG_CPU
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struct udevice *dev;
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char desc[32];
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uclass_find_first_device(UCLASS_CPU, &dev);
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if (!dev) {
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debug("unable to find the RISC-V cpu device\n");
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return false;
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}
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if (!cpu_get_desc(dev, desc, sizeof(desc))) {
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/* skip the first 4 characters (rv32|rv64) */
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if (strchr(desc + 4, ext))
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return true;
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}
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return false;
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#else /* !CONFIG_CPU */
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#ifdef CONFIG_RISCV_MMODE
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return csr_read(misa) & (1 << (ext - 'a'));
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#else /* !CONFIG_RISCV_MMODE */
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#warning "There is no way to determine the available extensions in S-mode."
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#warning "Please convert your board to use the RISC-V CPU driver."
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return false;
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#endif /* CONFIG_RISCV_MMODE */
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#endif /* CONFIG_CPU */
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}
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static int riscv_cpu_probe(void)
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{
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#ifdef CONFIG_CPU
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int ret;
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/* probe cpus so that RISC-V timer can be bound */
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ret = cpu_probe_all();
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if (ret)
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return log_msg_ret("RISC-V cpus probe failed\n", ret);
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#endif
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return 0;
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}
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int arch_cpu_init_dm(void)
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{
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return riscv_cpu_probe();
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}
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int arch_early_init_r(void)
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{
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return riscv_cpu_probe();
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}
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