mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 18:56:15 +09:00
86cf1c8285
We have the following cases: - CONFIG_NR_DRAM_BANKS was defined, migrate normally - CONFIG_NR_DRAM_BANKS_MAX was defined and then used for CONFIG_NR_DRAM_BANKS after a check, just migrate it over now. - CONFIG_NR_DRAM_BANKS was very oddly defined on p2771-0000-* (to 1024 + 2), set this to 8. Signed-off-by: Tom Rini <trini@konsulko.com>
95 lines
2.4 KiB
C
95 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2010-2012
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* NVIDIA Corporation <www.nvidia.com>
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*/
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#ifndef _TEGRA_COMMON_H_
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#define _TEGRA_COMMON_H_
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#include <linux/sizes.h>
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#include <linux/stringify.h>
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
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#include <asm/arch/tegra.h> /* get chip and board defs */
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/* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */
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#ifndef CONFIG_ARM64
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#define CONFIG_SYS_TIMER_RATE 1000000
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#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
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#endif
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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/* Environment */
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#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
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/*
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* NS16550 Configuration
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*/
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#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
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/*
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* Common HW configuration.
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* If this varies between SoCs later, move to tegraNN-common.h
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* Note: This is number of devices, not max device ID.
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*/
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#define CONFIG_SYS_MMC_MAX_DEVICE 4
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/*
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* select serial console configuration
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*/
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/* allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/* turn on command-line edit/hist/auto */
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/*
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* Increasing the size of the IO buffer as default nfsargs size is more
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* than 256 and so it is not possible to edit it
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*/
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#define CONFIG_SYS_CBSIZE (1024 * 2) /* Console I/O Buffer Size */
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/* Print Buffer Size */
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#define CONFIG_SYS_MAXARGS 64 /* max number of command args */
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/* Boot Argument Buffer Size */
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#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
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#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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*/
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#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
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#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
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#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
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#ifndef CONFIG_ARM64
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#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
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#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
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CONFIG_SYS_INIT_RAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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#endif
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#ifndef CONFIG_ARM64
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/* Defines for SPL */
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#define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \
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CONFIG_SPL_TEXT_BASE)
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
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#endif
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/* Misc utility code */
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#define CONFIG_BOUNCE_BUFFER
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#endif /* _TEGRA_COMMON_H_ */
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