mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 18:56:15 +09:00
86cf1c8285
We have the following cases: - CONFIG_NR_DRAM_BANKS was defined, migrate normally - CONFIG_NR_DRAM_BANKS_MAX was defined and then used for CONFIG_NR_DRAM_BANKS after a check, just migrate it over now. - CONFIG_NR_DRAM_BANKS was very oddly defined on p2771-0000-* (to 1024 + 2), set this to 8. Signed-off-by: Tom Rini <trini@konsulko.com>
52 lines
1.3 KiB
C
52 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2013-2016, NVIDIA CORPORATION.
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*/
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#ifndef _P2771_0000_H
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#define _P2771_0000_H
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#include <linux/sizes.h>
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#include "tegra186-common.h"
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/* High-level configuration options */
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#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2771-0000"
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/* I2C */
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#define CONFIG_SYS_I2C_TEGRA
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/* Environment in eMMC, at the end of 2nd "boot sector" */
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_SYS_MMC_ENV_PART 2
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#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
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/* PCI host support */
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#define BOARD_EXTRA_ENV_SETTINGS \
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"calculated_vars=kernel_addr_r fdt_addr_r scriptaddr pxefile_addr_r " \
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"ramdisk_addr_r\0" \
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"kernel_addr_r_align=00200000\0" \
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"kernel_addr_r_offset=00080000\0" \
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"kernel_addr_r_size=02000000\0" \
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"kernel_addr_r_aliases=loadaddr\0" \
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"fdt_addr_r_align=00200000\0" \
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"fdt_addr_r_offset=00000000\0" \
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"fdt_addr_r_size=00200000\0" \
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"scriptaddr_align=00200000\0" \
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"scriptaddr_offset=00000000\0" \
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"scriptaddr_size=00200000\0" \
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"pxefile_addr_r_align=00200000\0" \
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"pxefile_addr_r_offset=00000000\0" \
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"pxefile_addr_r_size=00200000\0" \
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"ramdisk_addr_r_align=00200000\0" \
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"ramdisk_addr_r_offset=00000000\0" \
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"ramdisk_addr_r_size=02000000\0"
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#include "tegra-common-post.h"
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/* Crystal is 38.4MHz. clk_m runs at half that rate */
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#define COUNTER_FREQUENCY 19200000
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#endif
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