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https://github.com/brain-hackers/u-boot-brain
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![Tien Fong Chee](/assets/img/avatar_default.png)
Replace CONFIG_SPL_EXT_SUPPORT to CONFIG_SPLY_FS_EXT4 so both obj-$(CONFIG_$(SPL_)FS_EXT4) and CONFIG_IS_ENABLED(FS_EXT4) can be used to control the build in both SPL and U-Boot. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Tom Rini <trini@konsulko.com>
201 lines
5.5 KiB
C
201 lines
5.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
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*
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*/
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#include <asm/io.h>
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#include <asm/u-boot.h>
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#include <asm/utils.h>
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#include <common.h>
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#include <debug_uart.h>
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#include <image.h>
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#include <spl.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/firewall_s10.h>
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#include <asm/arch/mailbox_s10.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/sdram_s10.h>
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#include <asm/arch/system_manager.h>
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#include <watchdog.h>
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DECLARE_GLOBAL_DATA_PTR;
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static struct socfpga_system_manager *sysmgr_regs =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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u32 spl_boot_device(void)
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{
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/* TODO: Get from SDM or handoff */
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return BOOT_DEVICE_MMC1;
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}
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#ifdef CONFIG_SPL_MMC_SUPPORT
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u32 spl_boot_mode(const u32 boot_device)
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{
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#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
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return MMCSD_MODE_FS;
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#else
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return MMCSD_MODE_RAW;
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#endif
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}
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#endif
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void spl_disable_firewall_l4_per(void)
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{
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const struct socfpga_firwall_l4_per *firwall_l4_per_base =
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(struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
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u32 i;
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const u32 *addr[] = {
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&firwall_l4_per_base->nand,
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&firwall_l4_per_base->nand_data,
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&firwall_l4_per_base->usb0,
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&firwall_l4_per_base->usb1,
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&firwall_l4_per_base->spim0,
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&firwall_l4_per_base->spim1,
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&firwall_l4_per_base->emac0,
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&firwall_l4_per_base->emac1,
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&firwall_l4_per_base->emac2,
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&firwall_l4_per_base->sdmmc,
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&firwall_l4_per_base->gpio0,
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&firwall_l4_per_base->gpio1,
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&firwall_l4_per_base->i2c0,
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&firwall_l4_per_base->i2c1,
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&firwall_l4_per_base->i2c2,
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&firwall_l4_per_base->i2c3,
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&firwall_l4_per_base->i2c4,
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&firwall_l4_per_base->timer0,
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&firwall_l4_per_base->timer1,
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&firwall_l4_per_base->uart0,
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&firwall_l4_per_base->uart1
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};
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/*
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* The following lines of code will enable non-secure access
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* to nand, usb, spi, emac, sdmmc, gpio, i2c, timers and uart. This
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* is needed as most OS run in non-secure mode. Thus we need to
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* enable non-secure access to these peripherals in order for the
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* OS to use these peripherals.
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*/
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for (i = 0; i < ARRAY_SIZE(addr); i++)
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writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
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}
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void spl_disable_firewall_l4_sys(void)
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{
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const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
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(struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;
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u32 i;
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const u32 *addr[] = {
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&firwall_l4_sys_base->dma_ecc,
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&firwall_l4_sys_base->emac0rx_ecc,
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&firwall_l4_sys_base->emac0tx_ecc,
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&firwall_l4_sys_base->emac1rx_ecc,
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&firwall_l4_sys_base->emac1tx_ecc,
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&firwall_l4_sys_base->emac2rx_ecc,
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&firwall_l4_sys_base->emac2tx_ecc,
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&firwall_l4_sys_base->nand_ecc,
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&firwall_l4_sys_base->nand_read_ecc,
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&firwall_l4_sys_base->nand_write_ecc,
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&firwall_l4_sys_base->ocram_ecc,
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&firwall_l4_sys_base->sdmmc_ecc,
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&firwall_l4_sys_base->usb0_ecc,
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&firwall_l4_sys_base->usb1_ecc,
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&firwall_l4_sys_base->clock_manager,
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&firwall_l4_sys_base->io_manager,
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&firwall_l4_sys_base->reset_manager,
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&firwall_l4_sys_base->system_manager,
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&firwall_l4_sys_base->watchdog0,
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&firwall_l4_sys_base->watchdog1,
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&firwall_l4_sys_base->watchdog2,
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&firwall_l4_sys_base->watchdog3
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};
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for (i = 0; i < ARRAY_SIZE(addr); i++)
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writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
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}
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void board_init_f(ulong dummy)
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{
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const struct cm_config *cm_default_cfg = cm_get_default_config();
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int ret;
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#ifdef CONFIG_HW_WATCHDOG
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/* Ensure watchdog is paused when debugging is happening */
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writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg);
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/* Enable watchdog before initializing the HW */
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socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
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socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
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hw_watchdog_init();
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#endif
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/* ensure all processors are not released prior Linux boot */
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writeq(0, CPU_RELEASE_ADDR);
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socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
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timer_init();
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sysmgr_pinmux_init();
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/* configuring the HPS clocks */
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cm_basic_init(cm_default_cfg);
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#ifdef CONFIG_DEBUG_UART
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socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
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debug_uart_init();
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#endif
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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preloader_console_init();
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cm_print_clock_quick_summary();
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/* enable non-secure interface to DMA330 DMA and peripherals */
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writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma);
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writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph);
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spl_disable_firewall_l4_per();
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spl_disable_firewall_l4_sys();
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/* disable lwsocf2fpga and soc2fpga bridge security */
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writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA);
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writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA);
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/* disable SMMU security */
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writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU);
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/* disable ocram security at CCU for non secure access */
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clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
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CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
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clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
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CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
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debug("DDR: Initializing Hard Memory Controller\n");
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if (sdram_mmr_init_full(0)) {
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puts("DDR: Initialization failed.\n");
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hang();
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}
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gd->ram_size = sdram_calculate_size();
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printf("DDR: %d MiB\n", (int)(gd->ram_size >> 20));
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/* Sanity check ensure correct SDRAM size specified */
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debug("DDR: Running SDRAM size sanity check\n");
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if (get_ram_size(0, gd->ram_size) != gd->ram_size) {
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puts("DDR: SDRAM size check failed!\n");
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hang();
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}
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debug("DDR: SDRAM size check passed!\n");
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mbox_init();
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#ifdef CONFIG_CADENCE_QSPI
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mbox_qspi_open();
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#endif
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}
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