mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 19:26:16 +09:00
7599b53dc1
Now that the SPL structure is organised such that it matches the U-Boot's SPL design, it is possible to use the option of relocating GD to RAM. And since we have GD in RAM, move malloc area to RAM as well. We point the malloc base pointer 1 MiB past U-Boot's load address. We use simple malloc for SPL because it is 3kiB smaller in terms of code size than regular malloc which was used thus far. Signed-off-by: Marek Vasut <marex@denx.de>
23 lines
531 B
Plaintext
23 lines
531 B
Plaintext
CONFIG_ARM=y
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CONFIG_ARCH_SOCFPGA=y
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CONFIG_TARGET_SOCFPGA_CYCLONE5=y
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CONFIG_DEFAULT_DEVICE_TREE="socfpga_cyclone5_socrates"
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CONFIG_SPL=y
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_FLASH is not set
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CONFIG_OF_CONTROL=y
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CONFIG_SPI_FLASH=y
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CONFIG_DM_ETH=y
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CONFIG_NETDEVICES=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_SPL_DM=y
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CONFIG_SPL_MMC_SUPPORT=y
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CONFIG_DM_SEQ_ALIAS=y
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CONFIG_SPL_SIMPLE_BUS=y
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CONFIG_DM_SPI=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SPL_SPI_SUPPORT=y
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CONFIG_SPL_STACK_R=y
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CONFIG_SPL_STACK_R_ADDR=0x00800000
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CONFIG_SYS_MALLOC_F_LEN=0x2000
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