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![Guochun Mao](/assets/img/avatar_default.png)
This patch adds MT7629 qspi driver for accessing SPI NOR flash. Signed-off-by: Guochun Mao <guochun.mao@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
360 lines
7.8 KiB
C
360 lines
7.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018 MediaTek, Inc.
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* Author : Guochun.Mao@mediatek.com
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*/
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#include <common.h>
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#include <dm.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/io.h>
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#include <linux/iopoll.h>
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#include <linux/ioport.h>
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/* Register Offset */
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struct mtk_qspi_regs {
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u32 cmd;
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u32 cnt;
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u32 rdsr;
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u32 rdata;
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u32 radr[3];
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u32 wdata;
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u32 prgdata[6];
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u32 shreg[10];
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u32 cfg[2];
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u32 shreg10;
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u32 mode_mon;
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u32 status[4];
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u32 flash_time;
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u32 flash_cfg;
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u32 reserved_0[3];
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u32 sf_time;
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u32 pp_dw_data;
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u32 reserved_1;
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u32 delsel_0[2];
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u32 intrstus;
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u32 intren;
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u32 reserved_2;
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u32 cfg3;
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u32 reserved_3;
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u32 chksum;
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u32 aaicmd;
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u32 wrprot;
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u32 radr3;
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u32 dual;
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u32 delsel_1[3];
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};
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struct mtk_qspi_platdata {
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fdt_addr_t reg_base;
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fdt_addr_t mem_base;
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};
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struct mtk_qspi_priv {
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struct mtk_qspi_regs *regs;
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unsigned long *mem_base;
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u8 op;
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u8 tx[3]; /* only record max 3 bytes paras, when it's address. */
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u32 txlen; /* dout buffer length - op code length */
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u8 *rx;
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u32 rxlen;
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};
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#define MTK_QSPI_CMD_POLLINGREG_US 500000
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#define MTK_QSPI_WRBUF_SIZE 256
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#define MTK_QSPI_COMMAND_ENABLE 0x30
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/* NOR flash controller commands */
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#define MTK_QSPI_RD_TRIGGER BIT(0)
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#define MTK_QSPI_READSTATUS BIT(1)
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#define MTK_QSPI_PRG_CMD BIT(2)
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#define MTK_QSPI_WR_TRIGGER BIT(4)
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#define MTK_QSPI_WRITESTATUS BIT(5)
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#define MTK_QSPI_AUTOINC BIT(7)
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#define MTK_QSPI_MAX_RX_TX_SHIFT 0x6
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#define MTK_QSPI_MAX_SHIFT 0x8
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#define MTK_QSPI_WR_BUF_ENABLE 0x1
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#define MTK_QSPI_WR_BUF_DISABLE 0x0
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static int mtk_qspi_execute_cmd(struct mtk_qspi_priv *priv, u8 cmd)
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{
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u8 tmp;
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u8 val = cmd & ~MTK_QSPI_AUTOINC;
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writeb(cmd, &priv->regs->cmd);
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return readb_poll_timeout(&priv->regs->cmd, tmp, !(val & tmp),
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MTK_QSPI_CMD_POLLINGREG_US);
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}
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static int mtk_qspi_tx_rx(struct mtk_qspi_priv *priv)
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{
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int len = 1 + priv->txlen + priv->rxlen;
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int i, ret, idx;
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if (len > MTK_QSPI_MAX_SHIFT)
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return -ERR_INVAL;
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writeb(len * 8, &priv->regs->cnt);
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/* start at PRGDATA5, go down to PRGDATA0 */
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idx = MTK_QSPI_MAX_RX_TX_SHIFT - 1;
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/* opcode */
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writeb(priv->op, &priv->regs->prgdata[idx]);
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idx--;
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/* program TX data */
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for (i = 0; i < priv->txlen; i++, idx--)
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writeb(priv->tx[i], &priv->regs->prgdata[idx]);
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/* clear out rest of TX registers */
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while (idx >= 0) {
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writeb(0, &priv->regs->prgdata[idx]);
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idx--;
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}
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ret = mtk_qspi_execute_cmd(priv, MTK_QSPI_PRG_CMD);
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if (ret)
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return ret;
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/* restart at first RX byte */
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idx = priv->rxlen - 1;
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/* read out RX data */
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for (i = 0; i < priv->rxlen; i++, idx--)
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priv->rx[i] = readb(&priv->regs->shreg[idx]);
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return 0;
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}
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static int mtk_qspi_read(struct mtk_qspi_priv *priv,
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u32 addr, u8 *buf, u32 len)
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{
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memcpy(buf, (u8 *)priv->mem_base + addr, len);
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return 0;
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}
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static void mtk_qspi_set_addr(struct mtk_qspi_priv *priv, u32 addr)
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{
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int i;
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for (i = 0; i < 3; i++) {
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writeb(addr & 0xff, &priv->regs->radr[i]);
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addr >>= 8;
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}
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}
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static int mtk_qspi_write_single_byte(struct mtk_qspi_priv *priv,
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u32 addr, u32 length, const u8 *data)
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{
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int i, ret;
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mtk_qspi_set_addr(priv, addr);
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for (i = 0; i < length; i++) {
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writeb(*data++, &priv->regs->wdata);
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ret = mtk_qspi_execute_cmd(priv, MTK_QSPI_WR_TRIGGER);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static int mtk_qspi_write_buffer(struct mtk_qspi_priv *priv, u32 addr,
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const u8 *buf)
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{
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int i, data;
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mtk_qspi_set_addr(priv, addr);
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for (i = 0; i < MTK_QSPI_WRBUF_SIZE; i += 4) {
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data = buf[i + 3] << 24 | buf[i + 2] << 16 |
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buf[i + 1] << 8 | buf[i];
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writel(data, &priv->regs->pp_dw_data);
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}
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return mtk_qspi_execute_cmd(priv, MTK_QSPI_WR_TRIGGER);
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}
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static int mtk_qspi_write(struct mtk_qspi_priv *priv,
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u32 addr, const u8 *buf, u32 len)
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{
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int ret;
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/* setting pre-fetch buffer for page program */
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writel(MTK_QSPI_WR_BUF_ENABLE, &priv->regs->cfg[1]);
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while (len >= MTK_QSPI_WRBUF_SIZE) {
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ret = mtk_qspi_write_buffer(priv, addr, buf);
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if (ret < 0)
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return ret;
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len -= MTK_QSPI_WRBUF_SIZE;
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addr += MTK_QSPI_WRBUF_SIZE;
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buf += MTK_QSPI_WRBUF_SIZE;
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}
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/* disable pre-fetch buffer for page program */
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writel(MTK_QSPI_WR_BUF_DISABLE, &priv->regs->cfg[1]);
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if (len)
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return mtk_qspi_write_single_byte(priv, addr, len, buf);
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return 0;
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}
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static int mtk_qspi_claim_bus(struct udevice *dev)
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{
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/* nothing to do */
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return 0;
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}
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static int mtk_qspi_release_bus(struct udevice *dev)
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{
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/* nothing to do */
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return 0;
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}
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static int mtk_qspi_transfer(struct mtk_qspi_priv *priv, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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u32 bytes = DIV_ROUND_UP(bitlen, 8);
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u32 addr;
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if (!bytes)
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return -ERR_INVAL;
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if (dout) {
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if (flags & SPI_XFER_BEGIN) {
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/* parse op code and potential paras first */
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priv->op = *(u8 *)dout;
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if (bytes > 1)
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memcpy(priv->tx, (u8 *)dout + 1,
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bytes <= 4 ? bytes - 1 : 3);
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priv->txlen = bytes - 1;
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}
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if (flags == SPI_XFER_ONCE) {
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/* operations without receiving or sending data.
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* for example: erase, write flash register or write
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* enable...
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*/
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priv->rx = NULL;
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priv->rxlen = 0;
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return mtk_qspi_tx_rx(priv);
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}
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if (flags & SPI_XFER_END) {
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/* here, dout should be data to be written.
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* and priv->tx should be filled 3Bytes address.
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*/
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addr = priv->tx[0] << 16 | priv->tx[1] << 8 |
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priv->tx[2];
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return mtk_qspi_write(priv, addr, (u8 *)dout, bytes);
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}
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}
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if (din) {
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if (priv->txlen >= 3) {
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/* if run to here, priv->tx[] should be the address
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* where read data from,
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* and, din is the buf to receive data.
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*/
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addr = priv->tx[0] << 16 | priv->tx[1] << 8 |
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priv->tx[2];
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return mtk_qspi_read(priv, addr, (u8 *)din, bytes);
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}
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/* should be reading flash's register */
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priv->rx = (u8 *)din;
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priv->rxlen = bytes;
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return mtk_qspi_tx_rx(priv);
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}
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return 0;
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}
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static int mtk_qspi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct mtk_qspi_priv *priv = dev_get_priv(bus);
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return mtk_qspi_transfer(priv, bitlen, dout, din, flags);
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}
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static int mtk_qspi_set_speed(struct udevice *bus, uint speed)
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{
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/* nothing to do */
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return 0;
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}
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static int mtk_qspi_set_mode(struct udevice *bus, uint mode)
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{
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/* nothing to do */
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return 0;
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}
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static int mtk_qspi_ofdata_to_platdata(struct udevice *bus)
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{
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struct resource res_reg, res_mem;
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struct mtk_qspi_platdata *plat = bus->platdata;
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int ret;
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ret = dev_read_resource_byname(bus, "reg_base", &res_reg);
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if (ret) {
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debug("can't get reg_base resource(ret = %d)\n", ret);
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return -ENOMEM;
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}
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ret = dev_read_resource_byname(bus, "mem_base", &res_mem);
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if (ret) {
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debug("can't get map_base resource(ret = %d)\n", ret);
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return -ENOMEM;
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}
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plat->mem_base = res_mem.start;
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plat->reg_base = res_reg.start;
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return 0;
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}
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static int mtk_qspi_probe(struct udevice *bus)
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{
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struct mtk_qspi_platdata *plat = dev_get_platdata(bus);
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struct mtk_qspi_priv *priv = dev_get_priv(bus);
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priv->regs = (struct mtk_qspi_regs *)plat->reg_base;
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priv->mem_base = (unsigned long *)plat->mem_base;
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writel(MTK_QSPI_COMMAND_ENABLE, &priv->regs->wrprot);
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return 0;
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}
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static const struct dm_spi_ops mtk_qspi_ops = {
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.claim_bus = mtk_qspi_claim_bus,
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.release_bus = mtk_qspi_release_bus,
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.xfer = mtk_qspi_xfer,
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.set_speed = mtk_qspi_set_speed,
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.set_mode = mtk_qspi_set_mode,
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};
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static const struct udevice_id mtk_qspi_ids[] = {
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{ .compatible = "mediatek,mt7629-qspi" },
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{ }
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};
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U_BOOT_DRIVER(mtk_qspi) = {
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.name = "mtk_qspi",
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.id = UCLASS_SPI,
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.of_match = mtk_qspi_ids,
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.ops = &mtk_qspi_ops,
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.ofdata_to_platdata = mtk_qspi_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct mtk_qspi_platdata),
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.priv_auto_alloc_size = sizeof(struct mtk_qspi_priv),
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.probe = mtk_qspi_probe,
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};
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