mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-12 15:53:21 +09:00
e895a4b06f
This function can fail if the device tree runs out of space. Rather than silently booting with an incomplete device tree, allow the failure to be detected. Unfortunately this involves changing a lot of places in the code. I have not changed behvaiour to return an error where one is not currently returned, to avoid unexpected breakage. Eventually it would be nice to allow boards to register functions to be called to update the device tree. This would avoid all the many functions to do this. However it's not clear yet if this should be done using driver model or with a linker list. This work is left for later. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
466 lines
9.9 KiB
C
466 lines
9.9 KiB
C
/*
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* Copyright 2009-2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <i2c.h>
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#include <netdev.h>
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#include <linux/compiler.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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#include <fm_eth.h>
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#include "../common/qixis.h"
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#include "../common/vsc3316_3308.h"
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#include "t208xqds.h"
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#include "t208xqds_qixis.h"
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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char buf[64];
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u8 sw;
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struct cpu_type *cpu = gd->arch.cpu;
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static const char *freq[4] = {
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"100.00MHZ(from 8T49N222A)", "125.00MHz",
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"156.25MHZ", "100.00MHz"
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};
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printf("Board: %sQDS, ", cpu->name);
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sw = QIXIS_READ(arch);
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printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
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printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
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#ifdef CONFIG_SDCARD
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puts("SD/MMC\n");
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#elif CONFIG_SPIFLASH
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puts("SPI\n");
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#else
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sw = QIXIS_READ(brdcfg[0]);
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sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
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if (sw < 0x8)
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printf("vBank%d\n", sw);
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else if (sw == 0x8)
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puts("Promjet\n");
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else if (sw == 0x9)
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puts("NAND\n");
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else
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printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
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#endif
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printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
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qixis_read_tag(buf), (int)qixis_read_minor());
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/* the timestamp string contains "\n" at the end */
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printf(" on %s", qixis_read_time(buf));
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puts("SERDES Reference Clocks:\n");
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sw = QIXIS_READ(brdcfg[2]);
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printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
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freq[(sw >> 4) & 0x3]);
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printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
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freq[sw & 0x3]);
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return 0;
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}
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int select_i2c_ch_pca9547(u8 ch)
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{
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int ret;
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ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
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if (ret) {
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puts("PCA: failed to select proper channel\n");
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return ret;
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}
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return 0;
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}
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int brd_mux_lane_to_slot(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 srds_prtcl_s1;
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srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
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srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
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#if defined(CONFIG_T2080QDS)
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u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
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srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
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#endif
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switch (srds_prtcl_s1) {
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case 0:
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/* SerDes1 is not enabled */
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break;
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#if defined(CONFIG_T2080QDS)
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case 0x1b:
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case 0x1c:
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case 0xa2:
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/* SD1(A:D) => SLOT3 SGMII
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* SD1(G:H) => SLOT1 SGMII
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*/
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QIXIS_WRITE(brdcfg[12], 0x1a);
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break;
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case 0x94:
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case 0x95:
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/* SD1(A:B) => SLOT3 SGMII@1.25bps
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* SD1(C:D) => SFP Module, SGMII@3.125bps
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* SD1(E:H) => SLOT1 SGMII@1.25bps
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*/
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case 0x96:
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/* SD1(A:B) => SLOT3 SGMII@1.25bps
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* SD1(C) => SFP Module, SGMII@3.125bps
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* SD1(D) => SFP Module, SGMII@1.25bps
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* SD1(E:H) => SLOT1 PCIe4 x4
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*/
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QIXIS_WRITE(brdcfg[12], 0x3a);
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break;
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case 0x50:
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case 0x51:
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/* SD1(A:D) => SLOT3 XAUI
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* SD1(E) => SLOT1 PCIe4
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* SD1(F:H) => SLOT2 SGMII
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*/
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QIXIS_WRITE(brdcfg[12], 0x15);
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break;
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case 0x66:
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case 0x67:
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/* SD1(A:D) => XFI cage
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* SD1(E:H) => SLOT1 PCIe4
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*/
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QIXIS_WRITE(brdcfg[12], 0xfe);
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break;
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case 0x6a:
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case 0x6b:
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/* SD1(A:D) => XFI cage
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* SD1(E) => SLOT1 PCIe4
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* SD1(F:H) => SLOT2 SGMII
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*/
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QIXIS_WRITE(brdcfg[12], 0xf1);
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break;
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case 0x6c:
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case 0x6d:
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/* SD1(A:B) => XFI cage
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* SD1(C:D) => SLOT3 SGMII
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* SD1(E:H) => SLOT1 PCIe4
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*/
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QIXIS_WRITE(brdcfg[12], 0xda);
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break;
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case 0x6e:
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/* SD1(A:B) => SFP Module, XFI
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* SD1(C:D) => SLOT3 SGMII
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* SD1(E:F) => SLOT1 PCIe4 x2
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* SD1(G:H) => SLOT2 SGMII
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*/
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QIXIS_WRITE(brdcfg[12], 0xd9);
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break;
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case 0xda:
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/* SD1(A:H) => SLOT3 PCIe3 x8
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*/
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QIXIS_WRITE(brdcfg[12], 0x0);
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break;
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case 0xc8:
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/* SD1(A) => SLOT3 PCIe3 x1
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* SD1(B) => SFP Module, SGMII@1.25bps
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* SD1(C:D) => SFP Module, SGMII@3.125bps
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* SD1(E:F) => SLOT1 PCIe4 x2
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* SD1(G:H) => SLOT2 SGMII
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*/
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QIXIS_WRITE(brdcfg[12], 0x79);
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break;
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case 0xab:
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/* SD1(A:D) => SLOT3 PCIe3 x4
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* SD1(E:H) => SLOT1 PCIe4 x4
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*/
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QIXIS_WRITE(brdcfg[12], 0x1a);
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break;
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#elif defined(CONFIG_T2081QDS)
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case 0x50:
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case 0x51:
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/* SD1(A:D) => SLOT2 XAUI
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* SD1(E) => SLOT1 PCIe4 x1
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* SD1(F:H) => SLOT3 SGMII
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*/
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QIXIS_WRITE(brdcfg[12], 0x98);
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QIXIS_WRITE(brdcfg[13], 0x70);
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break;
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case 0x6a:
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case 0x6b:
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/* SD1(A:D) => XFI SFP Module
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* SD1(E) => SLOT1 PCIe4 x1
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* SD1(F:H) => SLOT3 SGMII
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*/
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QIXIS_WRITE(brdcfg[12], 0x80);
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QIXIS_WRITE(brdcfg[13], 0x70);
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break;
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case 0x6c:
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case 0x6d:
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/* SD1(A:B) => XFI SFP Module
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* SD1(C:D) => SLOT2 SGMII
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* SD1(E:H) => SLOT1 PCIe4 x4
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*/
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QIXIS_WRITE(brdcfg[12], 0xe8);
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QIXIS_WRITE(brdcfg[13], 0x0);
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break;
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case 0xaa:
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case 0xab:
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/* SD1(A:D) => SLOT2 PCIe3 x4
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* SD1(F:H) => SLOT1 SGMI4 x4
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*/
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QIXIS_WRITE(brdcfg[12], 0xf8);
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QIXIS_WRITE(brdcfg[13], 0x0);
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break;
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case 0xca:
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case 0xcb:
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/* SD1(A) => SLOT2 PCIe3 x1
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* SD1(B) => SLOT7 SGMII
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* SD1(C) => SLOT6 SGMII
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* SD1(D) => SLOT5 SGMII
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* SD1(E) => SLOT1 PCIe4 x1
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* SD1(F:H) => SLOT3 SGMII
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*/
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QIXIS_WRITE(brdcfg[12], 0x80);
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QIXIS_WRITE(brdcfg[13], 0x70);
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break;
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case 0xde:
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case 0xdf:
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/* SD1(A:D) => SLOT2 PCIe3 x4
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* SD1(E) => SLOT1 PCIe4 x1
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* SD1(F) => SLOT4 PCIe1 x1
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* SD1(G) => SLOT3 PCIe2 x1
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* SD1(H) => SLOT7 SGMII
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*/
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QIXIS_WRITE(brdcfg[12], 0x98);
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QIXIS_WRITE(brdcfg[13], 0x25);
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break;
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case 0xf2:
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/* SD1(A) => SLOT2 PCIe3 x1
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* SD1(B:D) => SLOT7 SGMII
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* SD1(E) => SLOT1 PCIe4 x1
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* SD1(F) => SLOT4 PCIe1 x1
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* SD1(G) => SLOT3 PCIe2 x1
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* SD1(H) => SLOT7 SGMII
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*/
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QIXIS_WRITE(brdcfg[12], 0x81);
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QIXIS_WRITE(brdcfg[13], 0xa5);
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break;
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#endif
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default:
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printf("WARNING: unsupported for SerDes1 Protocol %d\n",
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srds_prtcl_s1);
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return -1;
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}
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#ifdef CONFIG_T2080QDS
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switch (srds_prtcl_s2) {
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case 0:
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/* SerDes2 is not enabled */
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break;
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case 0x01:
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case 0x02:
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/* SD2(A:H) => SLOT4 PCIe1 */
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QIXIS_WRITE(brdcfg[13], 0x10);
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break;
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case 0x15:
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case 0x16:
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/*
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* SD2(A:D) => SLOT4 PCIe1
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* SD2(E:F) => SLOT5 PCIe2
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* SD2(G:H) => SATA1,SATA2
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*/
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QIXIS_WRITE(brdcfg[13], 0xb0);
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break;
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case 0x18:
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/*
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* SD2(A:D) => SLOT4 PCIe1
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* SD2(E:F) => SLOT5 Aurora
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* SD2(G:H) => SATA1,SATA2
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*/
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QIXIS_WRITE(brdcfg[13], 0x78);
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break;
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case 0x1f:
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/*
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* SD2(A:D) => SLOT4 PCIe1
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* SD2(E:H) => SLOT5 PCIe2
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*/
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QIXIS_WRITE(brdcfg[13], 0xa0);
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break;
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case 0x29:
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case 0x2d:
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case 0x2e:
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/*
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* SD2(A:D) => SLOT4 SRIO2
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* SD2(E:H) => SLOT5 SRIO1
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*/
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QIXIS_WRITE(brdcfg[13], 0xa0);
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break;
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case 0x36:
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/*
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* SD2(A:D) => SLOT4 SRIO2
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* SD2(E:F) => Aurora
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* SD2(G:H) => SATA1,SATA2
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*/
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QIXIS_WRITE(brdcfg[13], 0x78);
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break;
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default:
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printf("WARNING: unsupported for SerDes2 Protocol %d\n",
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srds_prtcl_s2);
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return -1;
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}
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#endif
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return 0;
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}
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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int flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash + PROMJET region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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if (flash_esel == -1) {
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/* very unlikely unless something is messed up */
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puts("Error: Could not find TLB for FLASH BASE\n");
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flash_esel = 2; /* give our best effort to continue */
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} else {
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/* invalidate existing TLB entry for flash + promjet */
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disable_tlb(flash_esel);
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}
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_256M, 1);
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set_liodns();
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#ifdef CONFIG_SYS_DPAA_QBMAN
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setup_portals();
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#endif
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/* Disable remote I2C connection to qixis fpga */
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QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
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brd_mux_lane_to_slot();
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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return 0;
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}
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unsigned long get_board_sys_clk(void)
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{
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u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
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#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
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/* use accurate clock measurement */
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int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
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int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
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u32 val;
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val = freq * base;
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if (val) {
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debug("SYS Clock measurement is: %d\n", val);
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return val;
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} else {
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printf("Warning: SYS clock measurement is invalid, ");
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printf("using value from brdcfg1.\n");
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}
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#endif
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switch (sysclk_conf & 0x0F) {
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case QIXIS_SYSCLK_83:
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return 83333333;
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case QIXIS_SYSCLK_100:
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return 100000000;
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case QIXIS_SYSCLK_125:
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return 125000000;
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case QIXIS_SYSCLK_133:
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return 133333333;
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case QIXIS_SYSCLK_150:
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return 150000000;
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case QIXIS_SYSCLK_160:
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return 160000000;
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case QIXIS_SYSCLK_166:
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return 166666666;
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}
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return 66666666;
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}
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unsigned long get_board_ddr_clk(void)
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{
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u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
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#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
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/* use accurate clock measurement */
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int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
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int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
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u32 val;
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val = freq * base;
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if (val) {
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debug("DDR Clock measurement is: %d\n", val);
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return val;
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} else {
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printf("Warning: DDR clock measurement is invalid, ");
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printf("using value from brdcfg1.\n");
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}
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#endif
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switch ((ddrclk_conf & 0x30) >> 4) {
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case QIXIS_DDRCLK_100:
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return 100000000;
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case QIXIS_DDRCLK_125:
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return 125000000;
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case QIXIS_DDRCLK_133:
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return 133333333;
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}
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return 66666666;
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}
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int misc_init_r(void)
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{
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return 0;
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}
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int ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#ifdef CONFIG_PCI
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pci_of_setup(blob, bd);
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#endif
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fdt_fixup_liodn(blob);
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fdt_fixup_dr_usb(blob, bd);
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#ifdef CONFIG_SYS_DPAA_FMAN
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fdt_fixup_fman_ethernet(blob);
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fdt_fixup_board_enet(blob);
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#endif
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return 0;
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}
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