mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-26 20:09:02 +09:00
178 lines
4.5 KiB
C
178 lines
4.5 KiB
C
/*
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* (C) Copyright 2005
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <command.h>
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#include "p3p440.h"
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DECLARE_GLOBAL_DATA_PTR;
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void set_led(int color)
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{
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switch (color) {
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case LED_OFF:
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_LED_GREEN & ~CONFIG_SYS_LED_RED);
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break;
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case LED_GREEN:
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out32(GPIO0_OR, (in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN) & ~CONFIG_SYS_LED_RED);
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break;
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case LED_RED:
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out32(GPIO0_OR, (in32(GPIO0_OR) | CONFIG_SYS_LED_RED) & ~CONFIG_SYS_LED_GREEN);
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break;
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case LED_ORANGE:
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out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN | CONFIG_SYS_LED_RED);
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break;
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}
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}
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static int is_monarch(void)
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{
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_GPIO_RDY);
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udelay(1000);
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if (in32(GPIO0_IR) & CONFIG_SYS_MONARCH_IO)
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return 0;
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else
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return 1;
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}
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static void wait_for_pci_ready(void)
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{
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/*
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* Configure EREADY_IO as input
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*/
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out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_EREADY_IO);
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udelay(1000);
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for (;;) {
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if (in32(GPIO0_IR) & CONFIG_SYS_EREADY_IO)
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return;
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}
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}
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int board_early_init_f(void)
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{
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uint reg;
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/*--------------------------------------------------------------------
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* Setup the external bus controller/chip selects
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*-------------------------------------------------------------------*/
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mtdcr(EBC0_CFGADDR, EBC0_CFG);
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reg = mfdcr(EBC0_CFGDATA);
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mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */
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/*--------------------------------------------------------------------
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* Setup pin multiplexing (GPIO/IRQ...)
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*-------------------------------------------------------------------*/
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mtdcr(CPC0_GPIO, 0x03F01F80);
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out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
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out32(GPIO0_TCR, CONFIG_SYS_GPIO_RDY | CONFIG_SYS_EREADY_IO | CONFIG_SYS_LED_RED | CONFIG_SYS_LED_GREEN);
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out32(GPIO0_OR, CONFIG_SYS_GPIO_RDY);
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC0ER, 0x00000000); /* disable all */
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mtdcr(UIC0CR, 0x00000001); /* UIC1 crit is critical */
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mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */
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mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */
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mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC1ER, 0x00000000); /* disable all */
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mtdcr(UIC1CR, 0x00000000); /* all non-critical */
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mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */
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mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */
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mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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return 0;
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}
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int checkboard(void)
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{
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char buf[64];
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int i = getenv_f("serial#", buf, sizeof(buf));
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printf("Board: P3P440");
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if (i > 0) {
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puts(", serial# ");
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puts(buf);
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}
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if (is_monarch()) {
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puts(", Monarch");
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} else {
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puts(", None-Monarch");
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}
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putc('\n');
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return (0);
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}
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int misc_init_r (void)
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{
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/*
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* Adjust flash start and offset to detected values
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*/
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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/*
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* Check if only one FLASH bank is available
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*/
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if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
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mtebc(PB1CR, 0); /* disable cs */
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mtebc(PB1AP, 0);
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mtebc(PB2CR, 0); /* disable cs */
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mtebc(PB2AP, 0);
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mtebc(PB3CR, 0); /* disable cs */
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mtebc(PB3AP, 0);
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}
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return 0;
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}
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/*************************************************************************
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* Override weak is_pci_host()
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*
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* This routine is called to determine if a pci scan should be
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* performed. With various hardware environments (especially cPCI and
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* PPMC) it's insufficient to depend on the state of the arbiter enable
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* bit in the strap register, or generic host/adapter assumptions.
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*
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* Rather than hard-code a bad assumption in the general 440 code, the
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* 440 pci code requires the board to decide at runtime.
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*
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* Return 0 for adapter mode, non-zero for host (monarch) mode.
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*
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*
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************************************************************************/
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#if defined(CONFIG_PCI)
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int is_pci_host(struct pci_controller *hose)
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{
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if (is_monarch()) {
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wait_for_pci_ready();
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return 1; /* return 1 for host controller */
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} else {
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return 0; /* return 0 for adapter controller */
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}
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}
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#endif /* defined(CONFIG_PCI) */
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