mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 11:16:15 +09:00
e090579d0a
This commit removes definitions of CONFIG_SYS_BARGSIZE defined to be equal to CONFIG_SYS_CBSIZE in numerous configuration files. We remove such definitions in two situations: - CONFIG_SYS_CBSIZE is otherwise not defined in the board configuration file, which means the default value of CONFIG_SYS_CBSIZE == 256 applies. In this case, the default value of CONFIG_SYS_BARGSIZE == 512 (common/image.c) is suitable, as it is larger. - CONFIG_SYS_CBSIZE is defined in the board configuration file, but to a value equal or less than 512. In this case, the default value of CONFIG_SYS_BARGSIZE == 512 (common.image.c) is suitable, as it is equal or larger. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Reviewed-by: Tom Rini <trini@konsulko.com>
121 lines
3.1 KiB
C
121 lines
3.1 KiB
C
/*
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* Copyright 2016 Freescale Semiconductor
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __LS1012A_COMMON_H
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#define __LS1012A_COMMON_H
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#define CONFIG_FSL_LAYERSCAPE
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#define CONFIG_GICV2
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#include <asm/arch/config.h>
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#include <asm/arch/stream_id_lsch2.h>
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#define CONFIG_SUPPORT_RAW_INITRD
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#define CONFIG_DISPLAY_BOARDINFO_LATE
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#define CONFIG_SYS_TEXT_BASE 0x40100000
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#define CONFIG_SYS_CLK_FREQ 125000000
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
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/* Generic Timer Definitions */
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#define COUNTER_FREQUENCY CONFIG_SYS_CLK_FREQ/4 /* 25MHz */
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/* CSU */
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#define CONFIG_LAYERSCAPE_NS_ACCESS
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
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/*SPI device */
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#ifdef CONFIG_QSPI_BOOT
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#define CONFIG_SYS_QE_FW_IN_SPIFLASH
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#define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
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#define CONFIG_ENV_SPI_BUS 0
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#define CONFIG_ENV_SPI_CS 0
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#define CONFIG_ENV_SPI_MAX_HZ 1000000
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#define CONFIG_ENV_SPI_MODE 0x03
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#define CONFIG_SPI_FLASH_SPANSION
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#define CONFIG_FSL_SPI_INTERFACE
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#define CONFIG_SF_DATAFLASH
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#define CONFIG_FSL_QSPI
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#define QSPI0_AMBA_BASE 0x40000000
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#define CONFIG_SPI_FLASH_SPANSION
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#define FSL_QSPI_FLASH_SIZE SZ_64M
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#define FSL_QSPI_FLASH_NUM 2
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/*
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* Environment
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*/
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_SIZE 0x40000 /* 256KB */
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#define CONFIG_ENV_OFFSET 0x200000 /* 2MB */
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#define CONFIG_ENV_SECT_SIZE 0x40000
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#endif
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK (get_serial_clock())
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/* Command line configuration */
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#undef CONFIG_CMD_IMLS
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 128
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"verify=no\0" \
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"loadaddr=0x80100000\0" \
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"kernel_addr=0x100000\0" \
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"fdt_high=0xffffffffffffffff\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"kernel_start=0xa00000\0" \
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"kernel_load=0xa0000000\0" \
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"kernel_size=0x2800000\0" \
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#define CONFIG_BOOTCOMMAND "sf probe 0:0; sf read $kernel_load "\
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"$kernel_start $kernel_size && "\
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"bootm $kernel_load"
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_MAXARGS 64 /* max command args */
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#define CONFIG_PANIC_HANG
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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#include <asm/arch/soc.h>
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#endif /* __LS1012A_COMMON_H */
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