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https://github.com/brain-hackers/u-boot-brain
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a1f24875c3
The platform-Level Machine Timer (PLMT) block holds memory-mapped mtime register associated with timer tick. This driver implements the riscv_get_time() which is required by the generic RISC-V timer driver. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
20 lines
434 B
C
20 lines
434 B
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*/
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#ifndef _ASM_SYSCON_H
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#define _ASM_SYSCON_H
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/*
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* System controllers in a RISC-V system
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*/
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enum {
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RISCV_NONE,
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RISCV_SYSCON_CLINT, /* Core Local Interruptor (CLINT) */
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RISCV_SYSCON_PLIC, /* Platform Level Interrupt Controller (PLIC) */
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RISCV_SYSCON_PLMT, /* Platform Level Machine Timer (PLMT) */
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};
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#endif /* _ASM_SYSCON_H */
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