mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
445 lines
10 KiB
ArmAsm
445 lines
10 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Memory Setup stuff - taken from blob memsetup.S
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*
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* Copyright (C) 2009 Samsung Electronics
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* Kyungmin Park <kyungmin.park@samsung.com>
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*/
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#include <config.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/power.h>
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/*
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* Register usages:
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*
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* r5 has zero always
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* r7 has S5PC100 GPIO base, 0xE0300000
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* r8 has real GPIO base, 0xE0300000, 0xE0200000 at S5PC100, S5PC110 repectively
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* r9 has Mobile DDR size, 1 means 1GiB, 2 means 2GiB and so on
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*/
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.globl lowlevel_init
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lowlevel_init:
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mov r11, lr
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/* r5 has always zero */
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mov r5, #0
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ldr r7, =S5PC100_GPIO_BASE
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ldr r8, =S5PC100_GPIO_BASE
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/* Read CPU ID */
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ldr r2, =S5PC110_PRO_ID
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ldr r0, [r2]
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mov r1, #0x00010000
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and r0, r0, r1
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cmp r0, r5
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beq 100f
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ldr r8, =S5PC110_GPIO_BASE
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100:
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/* Turn on KEY_LED_ON [GPJ4(1)] XMSMWEN */
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cmp r7, r8
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beq skip_check_didle @ Support C110 only
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ldr r0, =S5PC110_RST_STAT
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ldr r1, [r0]
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and r1, r1, #0x000D0000
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cmp r1, #(0x1 << 19) @ DEEPIDLE_WAKEUP
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beq didle_wakeup
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cmp r7, r8
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skip_check_didle:
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addeq r0, r8, #0x280 @ S5PC100_GPIO_J4
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addne r0, r8, #0x2C0 @ S5PC110_GPIO_J4
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ldr r1, [r0, #0x0] @ GPIO_CON_OFFSET
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bic r1, r1, #(0xf << 4) @ 1 * 4-bit
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orr r1, r1, #(0x1 << 4)
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str r1, [r0, #0x0] @ GPIO_CON_OFFSET
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ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET
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bic r1, r1, #(1 << 1)
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str r1, [r0, #0x4] @ GPIO_DAT_OFFSET
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/* Don't setup at s5pc100 */
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beq 100f
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/*
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* Initialize Async Register Setting for EVT1
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* Because we are setting EVT1 as the default value of EVT0,
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* setting EVT0 as well does not make things worse.
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* Thus, for the simplicity, we set for EVT0, too
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*
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* The "Async Registers" are:
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* 0xE0F0_0000
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* 0xE1F0_0000
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* 0xF180_0000
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* 0xF190_0000
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* 0xF1A0_0000
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* 0xF1B0_0000
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* 0xF1C0_0000
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* 0xF1D0_0000
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* 0xF1E0_0000
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* 0xF1F0_0000
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* 0xFAF0_0000
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*/
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ldr r0, =0xe0f00000
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ldr r1, [r0]
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bic r1, r1, #0x1
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str r1, [r0]
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ldr r0, =0xe1f00000
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ldr r1, [r0]
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bic r1, r1, #0x1
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str r1, [r0]
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ldr r0, =0xf1800000
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ldr r1, [r0]
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bic r1, r1, #0x1
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str r1, [r0]
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ldr r0, =0xf1900000
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ldr r1, [r0]
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bic r1, r1, #0x1
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str r1, [r0]
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ldr r0, =0xf1a00000
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ldr r1, [r0]
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bic r1, r1, #0x1
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str r1, [r0]
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ldr r0, =0xf1b00000
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ldr r1, [r0]
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bic r1, r1, #0x1
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str r1, [r0]
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ldr r0, =0xf1c00000
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ldr r1, [r0]
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bic r1, r1, #0x1
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str r1, [r0]
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ldr r0, =0xf1d00000
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ldr r1, [r0]
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bic r1, r1, #0x1
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str r1, [r0]
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ldr r0, =0xf1e00000
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ldr r1, [r0]
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bic r1, r1, #0x1
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str r1, [r0]
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ldr r0, =0xf1f00000
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ldr r1, [r0]
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bic r1, r1, #0x1
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str r1, [r0]
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ldr r0, =0xfaf00000
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ldr r1, [r0]
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bic r1, r1, #0x1
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str r1, [r0]
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/*
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* Diable ABB block to reduce sleep current at low temperature
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* Note that it's hidden register setup don't modify it
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*/
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ldr r0, =0xE010C300
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ldr r1, =0x00800000
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str r1, [r0]
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100:
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/* IO retension release */
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ldreq r0, =S5PC100_OTHERS @ 0xE0108200
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ldrne r0, =S5PC110_OTHERS @ 0xE010E000
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ldr r1, [r0]
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ldreq r2, =(1 << 31) @ IO_RET_REL
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ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
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orr r1, r1, r2
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/* Do not release retention here for S5PC110 */
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streq r1, [r0]
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/* Disable Watchdog */
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ldreq r0, =S5PC100_WATCHDOG_BASE @ 0xEA200000
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ldrne r0, =S5PC110_WATCHDOG_BASE @ 0xE2700000
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str r5, [r0]
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/* setting SRAM */
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ldreq r0, =S5PC100_SROMC_BASE
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ldrne r0, =S5PC110_SROMC_BASE
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ldr r1, =0x9
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str r1, [r0]
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/* S5PC100 has 3 groups of interrupt sources */
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ldreq r0, =S5PC100_VIC0_BASE @ 0xE4000000
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ldrne r0, =S5PC110_VIC0_BASE @ 0xF2000000
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add r1, r0, #0x00100000
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add r2, r0, #0x00200000
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/* Disable all interrupts (VIC0, VIC1 and VIC2) */
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mvn r3, #0x0
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str r3, [r0, #0x14] @ INTENCLEAR
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str r3, [r1, #0x14] @ INTENCLEAR
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str r3, [r2, #0x14] @ INTENCLEAR
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/* Set all interrupts as IRQ */
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str r5, [r0, #0xc] @ INTSELECT
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str r5, [r1, #0xc] @ INTSELECT
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str r5, [r2, #0xc] @ INTSELECT
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/* Pending Interrupt Clear */
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str r5, [r0, #0xf00] @ INTADDRESS
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str r5, [r1, #0xf00] @ INTADDRESS
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str r5, [r2, #0xf00] @ INTADDRESS
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/* for UART */
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bl uart_asm_init
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bl internal_ram_init
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cmp r7, r8
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/* Clear wakeup status register */
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ldreq r0, =S5PC100_WAKEUP_STAT
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ldrne r0, =S5PC110_WAKEUP_STAT
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ldr r1, [r0]
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str r1, [r0]
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/* IO retension release */
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ldreq r0, =S5PC100_OTHERS @ 0xE0108200
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ldrne r0, =S5PC110_OTHERS @ 0xE010E000
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ldr r1, [r0]
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ldreq r2, =(1 << 31) @ IO_RET_REL
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ldrne r2, =((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28))
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orr r1, r1, r2
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str r1, [r0]
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b 1f
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didle_wakeup:
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/* Wait when APLL is locked */
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ldr r0, =0xE0100100 @ S5PC110_APLL_CON
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lockloop:
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ldr r1, [r0]
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and r1, r1, #(1 << 29)
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cmp r1, #(1 << 29)
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bne lockloop
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ldr r0, =S5PC110_INFORM0
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ldr r1, [r0]
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mov pc, r1
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nop
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nop
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nop
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nop
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nop
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1:
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mov lr, r11
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mov pc, lr
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/*
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* system_clock_init: Initialize core clock and bus clock.
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* void system_clock_init(void)
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*/
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system_clock_init:
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ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000
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/* Check S5PC100 */
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cmp r7, r8
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bne 110f
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100:
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/* Set Lock Time */
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ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
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str r1, [r0, #0x000] @ S5PC100_APLL_LOCK
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str r1, [r0, #0x004] @ S5PC100_MPLL_LOCK
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str r1, [r0, #0x008] @ S5PC100_EPLL_LOCK
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str r1, [r0, #0x00C] @ S5PC100_HPLL_LOCK
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/* S5P_APLL_CON */
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ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1333MHz)
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str r1, [r0, #0x100]
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/* S5P_MPLL_CON */
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ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
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str r1, [r0, #0x104]
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/* S5P_EPLL_CON */
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ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
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str r1, [r0, #0x108]
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/* S5P_HPLL_CON */
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ldr r1, =0x80600603 @ SDIV 3, PDIV 6, MDIV 96
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str r1, [r0, #0x10C]
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ldr r1, [r0, #0x300]
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ldr r2, =0x00003fff
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bic r1, r1, r2
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ldr r2, =0x00011301
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orr r1, r1, r2
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str r1, [r0, #0x300]
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ldr r1, [r0, #0x304]
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ldr r2, =0x00011110
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orr r1, r1, r2
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str r1, [r0, #0x304]
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ldr r1, =0x00000001
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str r1, [r0, #0x308]
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/* Set Source Clock */
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ldr r1, =0x00001111 @ A, M, E, HPLL Muxing
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str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
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b 200f
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110:
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ldr r0, =0xE010C000 @ S5PC110_PWR_CFG
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/* Set OSC_FREQ value */
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ldr r1, =0xf
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str r1, [r0, #0x100] @ S5PC110_OSC_FREQ
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/* Set MTC_STABLE value */
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ldr r1, =0xffffffff
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str r1, [r0, #0x110] @ S5PC110_MTC_STABLE
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/* Set CLAMP_STABLE value */
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ldr r1, =0x3ff03ff
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str r1, [r0, #0x114] @ S5PC110_CLAMP_STABLE
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ldr r0, =S5PC110_CLOCK_BASE @ 0xE0100000
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/* Set Clock divider */
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ldr r1, =0x14131330 @ 1:1:4:4, 1:4:5
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str r1, [r0, #0x300]
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ldr r1, =0x11110111 @ UART[3210]: MMC[3210]
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str r1, [r0, #0x310]
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/* Set Lock Time */
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ldr r1, =0x2cf @ Locktime : 30us
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str r1, [r0, #0x000] @ S5PC110_APLL_LOCK
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ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
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str r1, [r0, #0x008] @ S5PC110_MPLL_LOCK
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str r1, [r0, #0x010] @ S5PC110_EPLL_LOCK
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str r1, [r0, #0x020] @ S5PC110_VPLL_LOCK
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/* S5PC110_APLL_CON */
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ldr r1, =0x80C80601 @ 800MHz
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str r1, [r0, #0x100]
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/* S5PC110_MPLL_CON */
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ldr r1, =0x829B0C01 @ 667MHz
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str r1, [r0, #0x108]
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/* S5PC110_EPLL_CON */
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ldr r1, =0x80600602 @ 96MHz VSEL 0 P 6 M 96 S 2
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str r1, [r0, #0x110]
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/* S5PC110_VPLL_CON */
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ldr r1, =0x806C0603 @ 54MHz
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str r1, [r0, #0x120]
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/* Set Source Clock */
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ldr r1, =0x10001111 @ A, M, E, VPLL Muxing
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str r1, [r0, #0x200] @ S5PC1XX_CLK_SRC0
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/* OneDRAM(DMC0) clock setting */
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ldr r1, =0x01000000 @ ONEDRAM_SEL[25:24] 1 SCLKMPLL
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str r1, [r0, #0x218] @ S5PC110_CLK_SRC6
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ldr r1, =0x30000000 @ ONEDRAM_RATIO[31:28] 3 + 1
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str r1, [r0, #0x318] @ S5PC110_CLK_DIV6
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/* XCLKOUT = XUSBXTI 24MHz */
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add r2, r0, #0xE000 @ S5PC110_OTHERS
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ldr r1, [r2]
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orr r1, r1, #(0x3 << 8) @ CLKOUT[9:8] 3 XUSBXTI
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str r1, [r2]
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/* CLK_IP0 */
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ldr r1, =0x8fefeeb @ DMC[1:0] PDMA0[3] IMEM[5]
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str r1, [r0, #0x460] @ S5PC110_CLK_IP0
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/* CLK_IP1 */
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ldr r1, =0xe9fdf0f9 @ FIMD[0] USBOTG[16]
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@ NANDXL[24]
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str r1, [r0, #0x464] @ S5PC110_CLK_IP1
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/* CLK_IP2 */
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ldr r1, =0xf75f7fc @ CORESIGHT[8] MODEM[9]
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@ HOSTIF[10] HSMMC0[16]
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@ HSMMC2[18] VIC[27:24]
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str r1, [r0, #0x468] @ S5PC110_CLK_IP2
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/* CLK_IP3 */
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ldr r1, =0x8eff038c @ I2C[8:6]
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@ SYSTIMER[16] UART0[17]
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@ UART1[18] UART2[19]
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@ UART3[20] WDT[22]
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@ PWM[23] GPIO[26] SYSCON[27]
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str r1, [r0, #0x46c] @ S5PC110_CLK_IP3
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/* CLK_IP4 */
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ldr r1, =0xfffffff1 @ CHIP_ID[0] TZPC[8:5]
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str r1, [r0, #0x470] @ S5PC110_CLK_IP3
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200:
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/* wait at least 200us to stablize all clock */
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mov r2, #0x10000
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1: subs r2, r2, #1
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bne 1b
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mov pc, lr
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internal_ram_init:
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ldreq r0, =0xE3800000
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ldrne r0, =0xF1500000
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ldr r1, =0x0
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str r1, [r0]
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mov pc, lr
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/*
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* uart_asm_init: Initialize UART's pins
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*/
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uart_asm_init:
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/* set GPIO to enable UART0-UART4 */
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mov r0, r8
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ldr r1, =0x22222222
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str r1, [r0, #0x0] @ S5PC100_GPIO_A0_OFFSET
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ldr r1, =0x00002222
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str r1, [r0, #0x20] @ S5PC100_GPIO_A1_OFFSET
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/* Check S5PC100 */
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cmp r7, r8
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bne 110f
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/* UART_SEL GPK0[5] at S5PC100 */
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add r0, r8, #0x2A0 @ S5PC100_GPIO_K0_OFFSET
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ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
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bic r1, r1, #(0xf << 20) @ 20 = 5 * 4-bit
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orr r1, r1, #(0x1 << 20) @ Output
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str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
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ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
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bic r1, r1, #(0x3 << 10) @ 10 = 5 * 2-bit
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orr r1, r1, #(0x2 << 10) @ Pull-up enabled
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str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
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ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
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orr r1, r1, #(1 << 5) @ 5 = 5 * 1-bit
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str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
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b 200f
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110:
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/*
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* Note that the following address
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* 0xE020'0360 is reserved address at S5PC100
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*/
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/* UART_SEL MP0_5[7] at S5PC110 */
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add r0, r8, #0x360 @ S5PC110_GPIO_MP0_5_OFFSET
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ldr r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
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bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit
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orr r1, r1, #(0x1 << 28) @ Output
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str r1, [r0, #0x0] @ S5PC1XX_GPIO_CON_OFFSET
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ldr r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
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bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit
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orr r1, r1, #(0x2 << 14) @ Pull-up enabled
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str r1, [r0, #0x8] @ S5PC1XX_GPIO_PULL_OFFSET
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ldr r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
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orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit
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str r1, [r0, #0x4] @ S5PC1XX_GPIO_DAT_OFFSET
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200:
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mov pc, lr
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