mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-05 02:36:39 +09:00
05e7511fae
The patches changing the compatible strings to the ones used by Linux have not been merged yet, so fix the checks to use the current in-tree ones. Reported-by: Pali Rohár <pali@kernel.org> Signed-off-by: Andre Heider <a.heider@gmail.com> Reviewed-by: Pali Rohár <pali@kernel.org>
393 lines
11 KiB
C
393 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <dm.h>
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#include <env.h>
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#include <i2c.h>
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#include <init.h>
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#include <phy.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include <linux/delay.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* IO expander I2C device */
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#define I2C_IO_EXP_ADDR 0x22
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#define I2C_IO_CFG_REG_0 0x6
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#define I2C_IO_DATA_OUT_REG_0 0x2
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#define I2C_IO_REG_0_SATA_OFF 2
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#define I2C_IO_REG_0_USB_H_OFF 1
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/* The pin control values are the same for DB and Espressobin */
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#define PINCTRL_NB_REG_VALUE 0x000173fa
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#define PINCTRL_SB_REG_VALUE 0x00007a23
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/* Ethernet switch registers */
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/* SMI addresses for multi-chip mode */
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#define MVEBU_PORT_CTRL_SMI_ADDR(p) (16 + (p))
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#define MVEBU_SW_G2_SMI_ADDR (28)
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/* Multi-chip mode */
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#define MVEBU_SW_SMI_DATA_REG (1)
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#define MVEBU_SW_SMI_CMD_REG (0)
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#define SW_SMI_CMD_REG_ADDR_OFF 0
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#define SW_SMI_CMD_DEV_ADDR_OFF 5
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#define SW_SMI_CMD_SMI_OP_OFF 10
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#define SW_SMI_CMD_SMI_MODE_OFF 12
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#define SW_SMI_CMD_SMI_BUSY_OFF 15
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/* Single-chip mode */
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/* Switch Port Registers */
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#define MVEBU_SW_LINK_CTRL_REG (1)
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#define MVEBU_SW_PORT_CTRL_REG (4)
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#define MVEBU_SW_PORT_BASE_VLAN (6)
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/* Global 2 Registers */
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#define MVEBU_G2_SMI_PHY_CMD_REG (24)
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#define MVEBU_G2_SMI_PHY_DATA_REG (25)
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/*
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* Memory Controller Registers
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*
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* Assembled based on public information:
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* https://gitlab.nic.cz/turris/mox-boot-builder/-/blob/master/wtmi/main.c#L332-336
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* https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-18.12/drivers/mv_ddr_mc6.h#L309-L332
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*
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* And checked against the written register values for the various topologies:
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* https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/blob/mv_ddr-armada-atf-mainline/a3700/mv_ddr_tim.h
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*/
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#define A3700_CH0_MC_CTRL2_REG MVEBU_REGISTER(0x002c4)
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#define A3700_MC_CTRL2_SDRAM_TYPE_MASK 0xf
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#define A3700_MC_CTRL2_SDRAM_TYPE_OFFS 4
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#define A3700_MC_CTRL2_SDRAM_TYPE_DDR3 2
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#define A3700_MC_CTRL2_SDRAM_TYPE_DDR4 3
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int board_early_init_f(void)
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{
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return 0;
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}
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int board_init(void)
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{
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/* adress of boot parameters */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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bool ddr4, emmc;
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if (env_get("fdtfile"))
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return 0;
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if (!of_machine_is_compatible("marvell,armada-3720-espressobin"))
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return 0;
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/* If the memory controller has been configured for DDR4, we're running on v7 */
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ddr4 = ((readl(A3700_CH0_MC_CTRL2_REG) >> A3700_MC_CTRL2_SDRAM_TYPE_OFFS)
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& A3700_MC_CTRL2_SDRAM_TYPE_MASK) == A3700_MC_CTRL2_SDRAM_TYPE_DDR4;
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emmc = of_machine_is_compatible("marvell,armada-3720-espressobin-emmc");
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if (ddr4 && emmc)
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env_set("fdtfile", "marvell/armada-3720-espressobin-v7-emmc.dtb");
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else if (ddr4)
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env_set("fdtfile", "marvell/armada-3720-espressobin-v7.dtb");
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else if (emmc)
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env_set("fdtfile", "marvell/armada-3720-espressobin-emmc.dtb");
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else
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env_set("fdtfile", "marvell/armada-3720-espressobin.dtb");
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return 0;
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}
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#endif
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/* Board specific AHCI / SATA enable code */
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int board_ahci_enable(void)
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{
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struct udevice *dev;
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int ret;
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u8 buf[8];
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/* Only DB requres this configuration */
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if (!of_machine_is_compatible("marvell,armada-3720-db"))
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return 0;
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/* Configure IO exander PCA9555: 7bit address 0x22 */
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ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
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if (ret) {
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printf("Cannot find PCA9555: %d\n", ret);
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return 0;
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}
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ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
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if (ret) {
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printf("Failed to read IO expander value via I2C\n");
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return -EIO;
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}
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/*
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* Enable SATA power via IO expander connected via I2C by setting
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* the corresponding bit to output mode to enable power for SATA
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*/
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buf[0] &= ~(1 << I2C_IO_REG_0_SATA_OFF);
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ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
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if (ret) {
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printf("Failed to set IO expander via I2C\n");
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return -EIO;
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}
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return 0;
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}
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/* Board specific xHCI enable code */
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int board_xhci_enable(fdt_addr_t base)
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{
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struct udevice *dev;
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int ret;
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u8 buf[8];
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/* Only DB requres this configuration */
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if (!of_machine_is_compatible("marvell,armada-3720-db"))
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return 0;
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/* Configure IO exander PCA9555: 7bit address 0x22 */
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ret = i2c_get_chip_for_busnum(0, I2C_IO_EXP_ADDR, 1, &dev);
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if (ret) {
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printf("Cannot find PCA9555: %d\n", ret);
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return 0;
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}
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printf("Enable USB VBUS\n");
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/*
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* Read configuration (direction) and set VBUS pin as output
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* (reset pin = output)
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*/
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ret = dm_i2c_read(dev, I2C_IO_CFG_REG_0, buf, 1);
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if (ret) {
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printf("Failed to read IO expander value via I2C\n");
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return -EIO;
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}
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buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
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ret = dm_i2c_write(dev, I2C_IO_CFG_REG_0, buf, 1);
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if (ret) {
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printf("Failed to set IO expander via I2C\n");
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return -EIO;
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}
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/* Read VBUS output value and disable it */
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ret = dm_i2c_read(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
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if (ret) {
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printf("Failed to read IO expander value via I2C\n");
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return -EIO;
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}
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buf[0] &= ~(1 << I2C_IO_REG_0_USB_H_OFF);
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ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
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if (ret) {
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printf("Failed to set IO expander via I2C\n");
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return -EIO;
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}
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/*
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* Required delay for configuration to settle - must wait for
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* power on port is disabled in case VBUS signal was high,
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* required 3 seconds delay to let VBUS signal fully settle down
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*/
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mdelay(3000);
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/* Enable VBUS power: Set output value of VBUS pin as enabled */
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buf[0] |= (1 << I2C_IO_REG_0_USB_H_OFF);
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ret = dm_i2c_write(dev, I2C_IO_DATA_OUT_REG_0, buf, 1);
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if (ret) {
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printf("Failed to set IO expander via I2C\n");
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return -EIO;
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}
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mdelay(500); /* required delay to let output value settle */
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return 0;
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}
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/* Helper function for accessing switch devices in multi-chip connection mode */
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static int mii_multi_chip_mode_write(struct mii_dev *bus, int dev_smi_addr,
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int smi_addr, int reg, u16 value)
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{
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u16 smi_cmd = 0;
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if (bus->write(bus, dev_smi_addr, 0,
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MVEBU_SW_SMI_DATA_REG, value) != 0) {
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printf("Error writing to the PHY addr=%02x reg=%02x\n",
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smi_addr, reg);
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return -EFAULT;
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}
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smi_cmd = (1 << SW_SMI_CMD_SMI_BUSY_OFF) |
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(1 << SW_SMI_CMD_SMI_MODE_OFF) |
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(1 << SW_SMI_CMD_SMI_OP_OFF) |
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(smi_addr << SW_SMI_CMD_DEV_ADDR_OFF) |
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(reg << SW_SMI_CMD_REG_ADDR_OFF);
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if (bus->write(bus, dev_smi_addr, 0,
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MVEBU_SW_SMI_CMD_REG, smi_cmd) != 0) {
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printf("Error writing to the PHY addr=%02x reg=%02x\n",
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smi_addr, reg);
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return -EFAULT;
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}
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return 0;
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}
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/* Bring-up board-specific network stuff */
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int board_network_enable(struct mii_dev *bus)
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{
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if (!of_machine_is_compatible("marvell,armada-3720-espressobin"))
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return 0;
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/*
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* FIXME: remove this code once Topaz driver gets available
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* A3720 Community Board Only
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* Configure Topaz switch (88E6341)
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* Restrict output to ports 1,2,3 only from port 0 (CPU)
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* Set port 0,1,2,3 to forwarding Mode (through Switch Port registers)
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*/
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mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
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MVEBU_SW_PORT_BASE_VLAN, BIT(0));
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mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
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MVEBU_SW_PORT_BASE_VLAN, BIT(0));
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mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
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MVEBU_SW_PORT_BASE_VLAN, BIT(0));
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mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
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MVEBU_SW_PORT_CTRL_REG, 0x7f);
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mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(1),
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MVEBU_SW_PORT_CTRL_REG, 0x7f);
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mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(2),
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MVEBU_SW_PORT_CTRL_REG, 0x7f);
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mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(3),
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MVEBU_SW_PORT_CTRL_REG, 0x7f);
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/* RGMII Delay on Port 0 (CPU port), force link to 1000Mbps */
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mii_multi_chip_mode_write(bus, 1, MVEBU_PORT_CTRL_SMI_ADDR(0),
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MVEBU_SW_LINK_CTRL_REG, 0xe002);
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/* Power up PHY 1, 2, 3 (through Global 2 registers) */
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mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
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MVEBU_G2_SMI_PHY_DATA_REG, 0x1140);
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mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
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MVEBU_G2_SMI_PHY_CMD_REG, 0x9620);
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mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
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MVEBU_G2_SMI_PHY_CMD_REG, 0x9640);
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mii_multi_chip_mode_write(bus, 1, MVEBU_SW_G2_SMI_ADDR,
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MVEBU_G2_SMI_PHY_CMD_REG, 0x9660);
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return 0;
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}
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#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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int ret;
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int spi_off;
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int parts_off;
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int part_off;
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/* Fill SPI MTD partitions for Linux kernel on Espressobin */
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if (!of_machine_is_compatible("marvell,armada-3720-espressobin"))
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return 0;
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spi_off = fdt_node_offset_by_compatible(blob, -1, "jedec,spi-nor");
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if (spi_off < 0)
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return 0;
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/* Do not touch partitions if they are already defined */
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if (fdt_subnode_offset(blob, spi_off, "partitions") >= 0)
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return 0;
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parts_off = fdt_add_subnode(blob, spi_off, "partitions");
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if (parts_off < 0) {
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printf("Can't add partitions node: %s\n", fdt_strerror(parts_off));
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return 0;
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}
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ret = fdt_setprop_string(blob, parts_off, "compatible", "fixed-partitions");
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if (ret < 0) {
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printf("Can't set compatible property: %s\n", fdt_strerror(ret));
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return 0;
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}
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ret = fdt_setprop_u32(blob, parts_off, "#address-cells", 1);
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if (ret < 0) {
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printf("Can't set #address-cells property: %s\n", fdt_strerror(ret));
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return 0;
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}
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ret = fdt_setprop_u32(blob, parts_off, "#size-cells", 1);
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if (ret < 0) {
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printf("Can't set #size-cells property: %s\n", fdt_strerror(ret));
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return 0;
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}
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/* Add u-boot-env partition */
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part_off = fdt_add_subnode(blob, parts_off, "partition@u-boot-env");
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if (part_off < 0) {
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printf("Can't add partition@u-boot-env node: %s\n", fdt_strerror(part_off));
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return 0;
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}
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ret = fdt_setprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
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if (ret < 0) {
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printf("Can't set partition@u-boot-env reg property: %s\n", fdt_strerror(ret));
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return 0;
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}
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ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_SIZE);
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if (ret < 0) {
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printf("Can't set partition@u-boot-env reg property: %s\n", fdt_strerror(ret));
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return 0;
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}
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ret = fdt_setprop_string(blob, part_off, "label", "u-boot-env");
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if (ret < 0) {
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printf("Can't set partition@u-boot-env label property: %s\n", fdt_strerror(ret));
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return 0;
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}
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/* Add firmware partition */
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part_off = fdt_add_subnode(blob, parts_off, "partition@firmware");
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if (part_off < 0) {
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printf("Can't add partition@firmware node: %s\n", fdt_strerror(part_off));
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return 0;
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}
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ret = fdt_setprop_u32(blob, part_off, "reg", 0);
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if (ret < 0) {
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printf("Can't set partition@firmware reg property: %s\n", fdt_strerror(ret));
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return 0;
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}
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ret = fdt_appendprop_u32(blob, part_off, "reg", CONFIG_ENV_OFFSET);
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if (ret < 0) {
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printf("Can't set partition@firmware reg property: %s\n", fdt_strerror(ret));
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return 0;
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}
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ret = fdt_setprop_string(blob, part_off, "label", "firmware");
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if (ret < 0) {
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printf("Can't set partition@firmware label property: %s\n", fdt_strerror(ret));
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return 0;
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}
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return 0;
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}
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#endif
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