Paul Burton c5b8412d60 MIPS: Ensure Config.K0=2 applies before any memory accesses ... During boot we set Config.K0=2 (uncached) such that any accesses to the kseg0 memory region are performed uncached before the caches are initialised. This write to the Config register introduces an execution hazard between it & any following memory accesses (such as the load of _gp), which we need to clear in order to ensure those memory accesses are actually performed uncached. Clear this execution hazard with the insertion of an ehb execution hazard barrier instruction. Signed-off-by: Paul Burton <paul.burton@imgtec.com>		2016-09-21 15:04:04 +02:00
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mips32	MIPS: unify CPU code in arch/mips/cpu/	2015-01-30 14:19:58 +01:00
mips64	MIPS: unify CPU code in arch/mips/cpu/	2015-01-30 14:19:58 +01:00
cm_init.S	MIPS: Map CM Global Control Registers	2016-09-21 15:04:04 +02:00
cpu.c	MIPS: Probe cache line sizes once during boot	2016-09-21 15:04:04 +02:00
interrupts.c	MIPS: unify CPU code in arch/mips/cpu/	2015-01-30 14:19:58 +01:00
Makefile	MIPS: Map CM Global Control Registers	2016-09-21 15:04:04 +02:00
start.S	MIPS: Ensure Config.K0=2 applies before any memory accesses	2016-09-21 15:04:04 +02:00
time.c	MIPS: unify CPU code in arch/mips/cpu/	2015-01-30 14:19:58 +01:00
u-boot-spl.lds	MIPS: provide a default u-boot-spl.lds	2016-05-31 09:38:11 +02:00
u-boot.lds	MIPS: add .padding section to linker script	2014-11-01 18:18:05 +01:00