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https://github.com/brain-hackers/u-boot-brain
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![Stephen Warren](/assets/img/avatar_default.png)
This allows the USB code to determine whether a USB bus reset was issued, which in turn allows the code to differentiate between a detach (return to shell prompt) and a board reset/reboot request. Signed-off-by: Stephen Warren <swarren@nvidia.com>
929 lines
24 KiB
C
929 lines
24 KiB
C
/*
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* Copyright 2011, Marvell Semiconductor Inc.
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* Lei Wen <leiwen@marvell.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Back ported to the 8xx platform (from the 8260 platform) by
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* Murray.Jensen@cmst.csiro.au, 27-Jan-01.
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*/
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#include <common.h>
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#include <command.h>
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#include <config.h>
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#include <net.h>
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#include <malloc.h>
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#include <asm/byteorder.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <asm/unaligned.h>
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#include <linux/types.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <usb/ci_udc.h>
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#include "../host/ehci.h"
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#include "ci_udc.h"
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/*
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* Check if the system has too long cachelines. If the cachelines are
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* longer then 128b, the driver will not be able flush/invalidate data
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* cache over separate QH entries. We use 128b because one QH entry is
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* 64b long and there are always two QH list entries for each endpoint.
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*/
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#if ARCH_DMA_MINALIGN > 128
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#error This driver can not work on systems with caches longer than 128b
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#endif
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/*
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* Every QTD must be individually aligned, since we can program any
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* QTD's address into HW. Cache flushing requires ARCH_DMA_MINALIGN,
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* and the USB HW requires 32-byte alignment. Align to both:
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*/
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#define ILIST_ALIGN roundup(ARCH_DMA_MINALIGN, 32)
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/* Each QTD is this size */
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#define ILIST_ENT_RAW_SZ sizeof(struct ept_queue_item)
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/*
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* Align the size of the QTD too, so we can add this value to each
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* QTD's address to get another aligned address.
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*/
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#define ILIST_ENT_SZ roundup(ILIST_ENT_RAW_SZ, ILIST_ALIGN)
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/* For each endpoint, we need 2 QTDs, one for each of IN and OUT */
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#define ILIST_SZ (NUM_ENDPOINTS * 2 * ILIST_ENT_SZ)
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#ifndef DEBUG
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#define DBG(x...) do {} while (0)
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#else
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#define DBG(x...) printf(x)
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static const char *reqname(unsigned r)
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{
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switch (r) {
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case USB_REQ_GET_STATUS: return "GET_STATUS";
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case USB_REQ_CLEAR_FEATURE: return "CLEAR_FEATURE";
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case USB_REQ_SET_FEATURE: return "SET_FEATURE";
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case USB_REQ_SET_ADDRESS: return "SET_ADDRESS";
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case USB_REQ_GET_DESCRIPTOR: return "GET_DESCRIPTOR";
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case USB_REQ_SET_DESCRIPTOR: return "SET_DESCRIPTOR";
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case USB_REQ_GET_CONFIGURATION: return "GET_CONFIGURATION";
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case USB_REQ_SET_CONFIGURATION: return "SET_CONFIGURATION";
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case USB_REQ_GET_INTERFACE: return "GET_INTERFACE";
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case USB_REQ_SET_INTERFACE: return "SET_INTERFACE";
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default: return "*UNKNOWN*";
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}
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}
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#endif
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static struct usb_endpoint_descriptor ep0_desc = {
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.bLength = sizeof(struct usb_endpoint_descriptor),
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.bDescriptorType = USB_DT_ENDPOINT,
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.bEndpointAddress = USB_DIR_IN,
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.bmAttributes = USB_ENDPOINT_XFER_CONTROL,
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};
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static int ci_pullup(struct usb_gadget *gadget, int is_on);
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static int ci_ep_enable(struct usb_ep *ep,
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const struct usb_endpoint_descriptor *desc);
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static int ci_ep_disable(struct usb_ep *ep);
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static int ci_ep_queue(struct usb_ep *ep,
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struct usb_request *req, gfp_t gfp_flags);
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static struct usb_request *
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ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags);
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static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *_req);
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static struct usb_gadget_ops ci_udc_ops = {
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.pullup = ci_pullup,
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};
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static struct usb_ep_ops ci_ep_ops = {
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.enable = ci_ep_enable,
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.disable = ci_ep_disable,
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.queue = ci_ep_queue,
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.alloc_request = ci_ep_alloc_request,
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.free_request = ci_ep_free_request,
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};
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/* Init values for USB endpoints. */
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static const struct usb_ep ci_ep_init[2] = {
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[0] = { /* EP 0 */
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.maxpacket = 64,
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.name = "ep0",
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.ops = &ci_ep_ops,
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},
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[1] = { /* EP 1..n */
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.maxpacket = 512,
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.name = "ep-",
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.ops = &ci_ep_ops,
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},
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};
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static struct ci_drv controller = {
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.gadget = {
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.name = "ci_udc",
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.ops = &ci_udc_ops,
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.is_dualspeed = 1,
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},
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};
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/**
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* ci_get_qh() - return queue head for endpoint
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* @ep_num: Endpoint number
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* @dir_in: Direction of the endpoint (IN = 1, OUT = 0)
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*
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* This function returns the QH associated with particular endpoint
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* and it's direction.
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*/
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static struct ept_queue_head *ci_get_qh(int ep_num, int dir_in)
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{
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return &controller.epts[(ep_num * 2) + dir_in];
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}
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/**
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* ci_get_qtd() - return queue item for endpoint
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* @ep_num: Endpoint number
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* @dir_in: Direction of the endpoint (IN = 1, OUT = 0)
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*
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* This function returns the QH associated with particular endpoint
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* and it's direction.
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*/
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static struct ept_queue_item *ci_get_qtd(int ep_num, int dir_in)
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{
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int index = (ep_num * 2) + dir_in;
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uint8_t *imem = controller.items_mem + (index * ILIST_ENT_SZ);
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return (struct ept_queue_item *)imem;
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}
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/**
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* ci_flush_qh - flush cache over queue head
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* @ep_num: Endpoint number
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*
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* This function flushes cache over QH for particular endpoint.
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*/
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static void ci_flush_qh(int ep_num)
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{
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struct ept_queue_head *head = ci_get_qh(ep_num, 0);
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const uint32_t start = (uint32_t)head;
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const uint32_t end = start + 2 * sizeof(*head);
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flush_dcache_range(start, end);
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}
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/**
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* ci_invalidate_qh - invalidate cache over queue head
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* @ep_num: Endpoint number
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*
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* This function invalidates cache over QH for particular endpoint.
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*/
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static void ci_invalidate_qh(int ep_num)
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{
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struct ept_queue_head *head = ci_get_qh(ep_num, 0);
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uint32_t start = (uint32_t)head;
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uint32_t end = start + 2 * sizeof(*head);
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invalidate_dcache_range(start, end);
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}
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/**
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* ci_flush_qtd - flush cache over queue item
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* @ep_num: Endpoint number
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*
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* This function flushes cache over qTD pair for particular endpoint.
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*/
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static void ci_flush_qtd(int ep_num)
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{
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struct ept_queue_item *item = ci_get_qtd(ep_num, 0);
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const uint32_t start = (uint32_t)item;
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const uint32_t end = start + 2 * ILIST_ENT_SZ;
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flush_dcache_range(start, end);
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}
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/**
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* ci_invalidate_qtd - invalidate cache over queue item
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* @ep_num: Endpoint number
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*
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* This function invalidates cache over qTD pair for particular endpoint.
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*/
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static void ci_invalidate_qtd(int ep_num)
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{
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struct ept_queue_item *item = ci_get_qtd(ep_num, 0);
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const uint32_t start = (uint32_t)item;
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const uint32_t end = start + 2 * ILIST_ENT_SZ;
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invalidate_dcache_range(start, end);
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}
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static struct usb_request *
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ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags)
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{
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struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
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int num;
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struct ci_req *ci_req;
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num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
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if (num == 0 && controller.ep0_req)
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return &controller.ep0_req->req;
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ci_req = calloc(1, sizeof(*ci_req));
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if (!ci_req)
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return NULL;
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INIT_LIST_HEAD(&ci_req->queue);
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if (num == 0)
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controller.ep0_req = ci_req;
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return &ci_req->req;
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}
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static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *req)
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{
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struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
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struct ci_req *ci_req = container_of(req, struct ci_req, req);
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int num;
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num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
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if (num == 0) {
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if (!controller.ep0_req)
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return;
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controller.ep0_req = 0;
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}
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if (ci_req->b_buf)
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free(ci_req->b_buf);
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free(ci_req);
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}
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static void ep_enable(int num, int in, int maxpacket)
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{
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struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
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unsigned n;
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n = readl(&udc->epctrl[num]);
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if (in)
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n |= (CTRL_TXE | CTRL_TXR | CTRL_TXT_BULK);
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else
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n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK);
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if (num != 0) {
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struct ept_queue_head *head = ci_get_qh(num, in);
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head->config = CONFIG_MAX_PKT(maxpacket) | CONFIG_ZLT;
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ci_flush_qh(num);
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}
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writel(n, &udc->epctrl[num]);
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}
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static int ci_ep_enable(struct usb_ep *ep,
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const struct usb_endpoint_descriptor *desc)
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{
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struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
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int num, in;
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num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
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in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
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ci_ep->desc = desc;
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if (num) {
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int max = get_unaligned_le16(&desc->wMaxPacketSize);
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if ((max > 64) && (controller.gadget.speed == USB_SPEED_FULL))
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max = 64;
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if (ep->maxpacket != max) {
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DBG("%s: from %d to %d\n", __func__,
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ep->maxpacket, max);
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ep->maxpacket = max;
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}
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}
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ep_enable(num, in, ep->maxpacket);
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DBG("%s: num=%d maxpacket=%d\n", __func__, num, ep->maxpacket);
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return 0;
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}
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static int ci_ep_disable(struct usb_ep *ep)
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{
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struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
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ci_ep->desc = NULL;
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return 0;
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}
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static int ci_bounce(struct ci_req *ci_req, int in)
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{
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struct usb_request *req = &ci_req->req;
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uint32_t addr = (uint32_t)req->buf;
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uint32_t hwaddr;
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uint32_t aligned_used_len;
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/* Input buffer address is not aligned. */
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if (addr & (ARCH_DMA_MINALIGN - 1))
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goto align;
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/* Input buffer length is not aligned. */
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if (req->length & (ARCH_DMA_MINALIGN - 1))
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goto align;
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/* The buffer is well aligned, only flush cache. */
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ci_req->hw_len = req->length;
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ci_req->hw_buf = req->buf;
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goto flush;
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align:
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if (ci_req->b_buf && req->length > ci_req->b_len) {
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free(ci_req->b_buf);
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ci_req->b_buf = 0;
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}
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if (!ci_req->b_buf) {
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ci_req->b_len = roundup(req->length, ARCH_DMA_MINALIGN);
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ci_req->b_buf = memalign(ARCH_DMA_MINALIGN, ci_req->b_len);
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if (!ci_req->b_buf)
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return -ENOMEM;
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}
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ci_req->hw_len = ci_req->b_len;
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ci_req->hw_buf = ci_req->b_buf;
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if (in)
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memcpy(ci_req->hw_buf, req->buf, req->length);
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flush:
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hwaddr = (uint32_t)ci_req->hw_buf;
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aligned_used_len = roundup(req->length, ARCH_DMA_MINALIGN);
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flush_dcache_range(hwaddr, hwaddr + aligned_used_len);
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return 0;
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}
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static void ci_debounce(struct ci_req *ci_req, int in)
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{
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struct usb_request *req = &ci_req->req;
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uint32_t addr = (uint32_t)req->buf;
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uint32_t hwaddr = (uint32_t)ci_req->hw_buf;
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uint32_t aligned_used_len;
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if (in)
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return;
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aligned_used_len = roundup(req->actual, ARCH_DMA_MINALIGN);
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invalidate_dcache_range(hwaddr, hwaddr + aligned_used_len);
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if (addr == hwaddr)
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return; /* not a bounce */
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memcpy(req->buf, ci_req->hw_buf, req->actual);
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}
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static void ci_ep_submit_next_request(struct ci_ep *ci_ep)
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{
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struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
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struct ept_queue_item *item;
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struct ept_queue_head *head;
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int bit, num, len, in;
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struct ci_req *ci_req;
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ci_ep->req_primed = true;
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num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
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in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
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item = ci_get_qtd(num, in);
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head = ci_get_qh(num, in);
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ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue);
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len = ci_req->req.length;
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item->info = INFO_BYTES(len) | INFO_ACTIVE;
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item->page0 = (uint32_t)ci_req->hw_buf;
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item->page1 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x1000;
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item->page2 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x2000;
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item->page3 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x3000;
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item->page4 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x4000;
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head->next = (unsigned) item;
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head->info = 0;
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/*
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* When sending the data for an IN transaction, the attached host
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* knows that all data for the IN is sent when one of the following
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* occurs:
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* a) A zero-length packet is transmitted.
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* b) A packet with length that isn't an exact multiple of the ep's
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* maxpacket is transmitted.
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* c) Enough data is sent to exactly fill the host's maximum expected
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* IN transaction size.
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*
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* One of these conditions MUST apply at the end of an IN transaction,
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* or the transaction will not be considered complete by the host. If
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* none of (a)..(c) already applies, then we must force (a) to apply
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* by explicitly sending an extra zero-length packet.
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*/
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/* IN !a !b !c */
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if (in && len && !(len % ci_ep->ep.maxpacket) && ci_req->req.zero) {
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/*
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* Each endpoint has 2 items allocated, even though typically
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* only 1 is used at a time since either an IN or an OUT but
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* not both is queued. For an IN transaction, item currently
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* points at the second of these items, so we know that we
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* can use the other to transmit the extra zero-length packet.
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*/
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struct ept_queue_item *other_item = ci_get_qtd(num, 0);
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item->next = (unsigned)other_item;
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item = other_item;
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item->info = INFO_ACTIVE;
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}
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item->next = TERMINATE;
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item->info |= INFO_IOC;
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ci_flush_qtd(num);
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DBG("ept%d %s queue len %x, req %p, buffer %p\n",
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num, in ? "in" : "out", len, ci_req, ci_req->hw_buf);
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ci_flush_qh(num);
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|
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if (in)
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bit = EPT_TX(num);
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else
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bit = EPT_RX(num);
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writel(bit, &udc->epprime);
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}
|
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|
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static int ci_ep_queue(struct usb_ep *ep,
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struct usb_request *req, gfp_t gfp_flags)
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{
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struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
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struct ci_req *ci_req = container_of(req, struct ci_req, req);
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int in, ret;
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int __maybe_unused num;
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num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
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in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
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|
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if (!num && ci_ep->req_primed) {
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/*
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* The flipping of ep0 between IN and OUT relies on
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* ci_ep_queue consuming the current IN/OUT setting
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* immediately. If this is deferred to a later point when the
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* req is pulled out of ci_req->queue, then the IN/OUT setting
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|
* may have been changed since the req was queued, and state
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* will get out of sync. This condition doesn't occur today,
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* but could if bugs were introduced later, and this error
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|
* check will save a lot of debugging time.
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*/
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printf("%s: ep0 transaction already in progress\n", __func__);
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return -EPROTO;
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|
}
|
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|
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ret = ci_bounce(ci_req, in);
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if (ret)
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return ret;
|
|
|
|
DBG("ept%d %s pre-queue req %p, buffer %p\n",
|
|
num, in ? "in" : "out", ci_req, ci_req->hw_buf);
|
|
list_add_tail(&ci_req->queue, &ci_ep->queue);
|
|
|
|
if (!ci_ep->req_primed)
|
|
ci_ep_submit_next_request(ci_ep);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void flip_ep0_direction(void)
|
|
{
|
|
if (ep0_desc.bEndpointAddress == USB_DIR_IN) {
|
|
DBG("%s: Flipping ep0 to OUT\n", __func__);
|
|
ep0_desc.bEndpointAddress = 0;
|
|
} else {
|
|
DBG("%s: Flipping ep0 to IN\n", __func__);
|
|
ep0_desc.bEndpointAddress = USB_DIR_IN;
|
|
}
|
|
}
|
|
|
|
static void handle_ep_complete(struct ci_ep *ci_ep)
|
|
{
|
|
struct ept_queue_item *item;
|
|
int num, in, len;
|
|
struct ci_req *ci_req;
|
|
|
|
num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
|
|
in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
|
|
item = ci_get_qtd(num, in);
|
|
ci_invalidate_qtd(num);
|
|
|
|
len = (item->info >> 16) & 0x7fff;
|
|
if (item->info & 0xff)
|
|
printf("EP%d/%s FAIL info=%x pg0=%x\n",
|
|
num, in ? "in" : "out", item->info, item->page0);
|
|
|
|
ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue);
|
|
list_del_init(&ci_req->queue);
|
|
ci_ep->req_primed = false;
|
|
|
|
if (!list_empty(&ci_ep->queue))
|
|
ci_ep_submit_next_request(ci_ep);
|
|
|
|
ci_req->req.actual = ci_req->req.length - len;
|
|
ci_debounce(ci_req, in);
|
|
|
|
DBG("ept%d %s req %p, complete %x\n",
|
|
num, in ? "in" : "out", ci_req, len);
|
|
if (num != 0 || controller.ep0_data_phase)
|
|
ci_req->req.complete(&ci_ep->ep, &ci_req->req);
|
|
if (num == 0 && controller.ep0_data_phase) {
|
|
/*
|
|
* Data Stage is complete, so flip ep0 dir for Status Stage,
|
|
* which always transfers a packet in the opposite direction.
|
|
*/
|
|
DBG("%s: flip ep0 dir for Status Stage\n", __func__);
|
|
flip_ep0_direction();
|
|
controller.ep0_data_phase = false;
|
|
ci_req->req.length = 0;
|
|
usb_ep_queue(&ci_ep->ep, &ci_req->req, 0);
|
|
}
|
|
}
|
|
|
|
#define SETUP(type, request) (((type) << 8) | (request))
|
|
|
|
static void handle_setup(void)
|
|
{
|
|
struct ci_ep *ci_ep = &controller.ep[0];
|
|
struct ci_req *ci_req;
|
|
struct usb_request *req;
|
|
struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
|
|
struct ept_queue_head *head;
|
|
struct usb_ctrlrequest r;
|
|
int status = 0;
|
|
int num, in, _num, _in, i;
|
|
char *buf;
|
|
|
|
ci_req = controller.ep0_req;
|
|
req = &ci_req->req;
|
|
head = ci_get_qh(0, 0); /* EP0 OUT */
|
|
|
|
ci_invalidate_qh(0);
|
|
memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest));
|
|
#ifdef CONFIG_CI_UDC_HAS_HOSTPC
|
|
writel(EPT_RX(0), &udc->epsetupstat);
|
|
#else
|
|
writel(EPT_RX(0), &udc->epstat);
|
|
#endif
|
|
DBG("handle setup %s, %x, %x index %x value %x length %x\n",
|
|
reqname(r.bRequest), r.bRequestType, r.bRequest, r.wIndex,
|
|
r.wValue, r.wLength);
|
|
|
|
/* Set EP0 dir for Data Stage based on Setup Stage data */
|
|
if (r.bRequestType & USB_DIR_IN) {
|
|
DBG("%s: Set ep0 to IN for Data Stage\n", __func__);
|
|
ep0_desc.bEndpointAddress = USB_DIR_IN;
|
|
} else {
|
|
DBG("%s: Set ep0 to OUT for Data Stage\n", __func__);
|
|
ep0_desc.bEndpointAddress = 0;
|
|
}
|
|
if (r.wLength) {
|
|
controller.ep0_data_phase = true;
|
|
} else {
|
|
/* 0 length -> no Data Stage. Flip dir for Status Stage */
|
|
DBG("%s: 0 length: flip ep0 dir for Status Stage\n", __func__);
|
|
flip_ep0_direction();
|
|
controller.ep0_data_phase = false;
|
|
}
|
|
|
|
list_del_init(&ci_req->queue);
|
|
ci_ep->req_primed = false;
|
|
|
|
switch (SETUP(r.bRequestType, r.bRequest)) {
|
|
case SETUP(USB_RECIP_ENDPOINT, USB_REQ_CLEAR_FEATURE):
|
|
_num = r.wIndex & 15;
|
|
_in = !!(r.wIndex & 0x80);
|
|
|
|
if ((r.wValue == 0) && (r.wLength == 0)) {
|
|
req->length = 0;
|
|
for (i = 0; i < NUM_ENDPOINTS; i++) {
|
|
struct ci_ep *ep = &controller.ep[i];
|
|
|
|
if (!ep->desc)
|
|
continue;
|
|
num = ep->desc->bEndpointAddress
|
|
& USB_ENDPOINT_NUMBER_MASK;
|
|
in = (ep->desc->bEndpointAddress
|
|
& USB_DIR_IN) != 0;
|
|
if ((num == _num) && (in == _in)) {
|
|
ep_enable(num, in, ep->ep.maxpacket);
|
|
usb_ep_queue(controller.gadget.ep0,
|
|
req, 0);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
return;
|
|
|
|
case SETUP(USB_RECIP_DEVICE, USB_REQ_SET_ADDRESS):
|
|
/*
|
|
* write address delayed (will take effect
|
|
* after the next IN txn)
|
|
*/
|
|
writel((r.wValue << 25) | (1 << 24), &udc->devaddr);
|
|
req->length = 0;
|
|
usb_ep_queue(controller.gadget.ep0, req, 0);
|
|
return;
|
|
|
|
case SETUP(USB_DIR_IN | USB_RECIP_DEVICE, USB_REQ_GET_STATUS):
|
|
req->length = 2;
|
|
buf = (char *)req->buf;
|
|
buf[0] = 1 << USB_DEVICE_SELF_POWERED;
|
|
buf[1] = 0;
|
|
usb_ep_queue(controller.gadget.ep0, req, 0);
|
|
return;
|
|
}
|
|
/* pass request up to the gadget driver */
|
|
if (controller.driver)
|
|
status = controller.driver->setup(&controller.gadget, &r);
|
|
else
|
|
status = -ENODEV;
|
|
|
|
if (!status)
|
|
return;
|
|
DBG("STALL reqname %s type %x value %x, index %x\n",
|
|
reqname(r.bRequest), r.bRequestType, r.wValue, r.wIndex);
|
|
writel((1<<16) | (1 << 0), &udc->epctrl[0]);
|
|
}
|
|
|
|
static void stop_activity(void)
|
|
{
|
|
int i, num, in;
|
|
struct ept_queue_head *head;
|
|
struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
|
|
writel(readl(&udc->epcomp), &udc->epcomp);
|
|
#ifdef CONFIG_CI_UDC_HAS_HOSTPC
|
|
writel(readl(&udc->epsetupstat), &udc->epsetupstat);
|
|
#endif
|
|
writel(readl(&udc->epstat), &udc->epstat);
|
|
writel(0xffffffff, &udc->epflush);
|
|
|
|
/* error out any pending reqs */
|
|
for (i = 0; i < NUM_ENDPOINTS; i++) {
|
|
if (i != 0)
|
|
writel(0, &udc->epctrl[i]);
|
|
if (controller.ep[i].desc) {
|
|
num = controller.ep[i].desc->bEndpointAddress
|
|
& USB_ENDPOINT_NUMBER_MASK;
|
|
in = (controller.ep[i].desc->bEndpointAddress
|
|
& USB_DIR_IN) != 0;
|
|
head = ci_get_qh(num, in);
|
|
head->info = INFO_ACTIVE;
|
|
ci_flush_qh(num);
|
|
}
|
|
}
|
|
}
|
|
|
|
void udc_irq(void)
|
|
{
|
|
struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
|
|
unsigned n = readl(&udc->usbsts);
|
|
writel(n, &udc->usbsts);
|
|
int bit, i, num, in;
|
|
|
|
n &= (STS_SLI | STS_URI | STS_PCI | STS_UI | STS_UEI);
|
|
if (n == 0)
|
|
return;
|
|
|
|
if (n & STS_URI) {
|
|
DBG("-- reset --\n");
|
|
stop_activity();
|
|
}
|
|
if (n & STS_SLI)
|
|
DBG("-- suspend --\n");
|
|
|
|
if (n & STS_PCI) {
|
|
int max = 64;
|
|
int speed = USB_SPEED_FULL;
|
|
|
|
#ifdef CONFIG_CI_UDC_HAS_HOSTPC
|
|
bit = (readl(&udc->hostpc1_devlc) >> 25) & 3;
|
|
#else
|
|
bit = (readl(&udc->portsc) >> 26) & 3;
|
|
#endif
|
|
DBG("-- portchange %x %s\n", bit, (bit == 2) ? "High" : "Full");
|
|
if (bit == 2) {
|
|
speed = USB_SPEED_HIGH;
|
|
max = 512;
|
|
}
|
|
controller.gadget.speed = speed;
|
|
for (i = 1; i < NUM_ENDPOINTS; i++) {
|
|
if (controller.ep[i].ep.maxpacket > max)
|
|
controller.ep[i].ep.maxpacket = max;
|
|
}
|
|
}
|
|
|
|
if (n & STS_UEI)
|
|
printf("<UEI %x>\n", readl(&udc->epcomp));
|
|
|
|
if ((n & STS_UI) || (n & STS_UEI)) {
|
|
#ifdef CONFIG_CI_UDC_HAS_HOSTPC
|
|
n = readl(&udc->epsetupstat);
|
|
#else
|
|
n = readl(&udc->epstat);
|
|
#endif
|
|
if (n & EPT_RX(0))
|
|
handle_setup();
|
|
|
|
n = readl(&udc->epcomp);
|
|
if (n != 0)
|
|
writel(n, &udc->epcomp);
|
|
|
|
for (i = 0; i < NUM_ENDPOINTS && n; i++) {
|
|
if (controller.ep[i].desc) {
|
|
num = controller.ep[i].desc->bEndpointAddress
|
|
& USB_ENDPOINT_NUMBER_MASK;
|
|
in = (controller.ep[i].desc->bEndpointAddress
|
|
& USB_DIR_IN) != 0;
|
|
bit = (in) ? EPT_TX(num) : EPT_RX(num);
|
|
if (n & bit)
|
|
handle_ep_complete(&controller.ep[i]);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
int usb_gadget_handle_interrupts(void)
|
|
{
|
|
u32 value;
|
|
struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
|
|
|
|
value = readl(&udc->usbsts);
|
|
if (value)
|
|
udc_irq();
|
|
|
|
return value;
|
|
}
|
|
|
|
void udc_disconnect(void)
|
|
{
|
|
struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
|
|
/* disable pullup */
|
|
stop_activity();
|
|
writel(USBCMD_FS2, &udc->usbcmd);
|
|
udelay(800);
|
|
if (controller.driver)
|
|
controller.driver->disconnect(&controller.gadget);
|
|
}
|
|
|
|
static int ci_pullup(struct usb_gadget *gadget, int is_on)
|
|
{
|
|
struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
|
|
if (is_on) {
|
|
/* RESET */
|
|
writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd);
|
|
udelay(200);
|
|
|
|
writel((unsigned)controller.epts, &udc->epinitaddr);
|
|
|
|
/* select DEVICE mode */
|
|
writel(USBMODE_DEVICE, &udc->usbmode);
|
|
|
|
writel(0xffffffff, &udc->epflush);
|
|
|
|
/* Turn on the USB connection by enabling the pullup resistor */
|
|
writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RUN, &udc->usbcmd);
|
|
} else {
|
|
udc_disconnect();
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ci_udc_probe(void)
|
|
{
|
|
struct ept_queue_head *head;
|
|
int i;
|
|
|
|
const int num = 2 * NUM_ENDPOINTS;
|
|
|
|
const int eplist_min_align = 4096;
|
|
const int eplist_align = roundup(eplist_min_align, ARCH_DMA_MINALIGN);
|
|
const int eplist_raw_sz = num * sizeof(struct ept_queue_head);
|
|
const int eplist_sz = roundup(eplist_raw_sz, ARCH_DMA_MINALIGN);
|
|
|
|
/* The QH list must be aligned to 4096 bytes. */
|
|
controller.epts = memalign(eplist_align, eplist_sz);
|
|
if (!controller.epts)
|
|
return -ENOMEM;
|
|
memset(controller.epts, 0, eplist_sz);
|
|
|
|
controller.items_mem = memalign(ILIST_ALIGN, ILIST_SZ);
|
|
if (!controller.items_mem) {
|
|
free(controller.epts);
|
|
return -ENOMEM;
|
|
}
|
|
memset(controller.items_mem, 0, ILIST_SZ);
|
|
|
|
for (i = 0; i < 2 * NUM_ENDPOINTS; i++) {
|
|
/*
|
|
* Configure QH for each endpoint. The structure of the QH list
|
|
* is such that each two subsequent fields, N and N+1 where N is
|
|
* even, in the QH list represent QH for one endpoint. The Nth
|
|
* entry represents OUT configuration and the N+1th entry does
|
|
* represent IN configuration of the endpoint.
|
|
*/
|
|
head = controller.epts + i;
|
|
if (i < 2)
|
|
head->config = CONFIG_MAX_PKT(EP0_MAX_PACKET_SIZE)
|
|
| CONFIG_ZLT | CONFIG_IOS;
|
|
else
|
|
head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE)
|
|
| CONFIG_ZLT;
|
|
head->next = TERMINATE;
|
|
head->info = 0;
|
|
|
|
if (i & 1) {
|
|
ci_flush_qh(i / 2);
|
|
ci_flush_qtd(i / 2);
|
|
}
|
|
}
|
|
|
|
INIT_LIST_HEAD(&controller.gadget.ep_list);
|
|
|
|
/* Init EP 0 */
|
|
memcpy(&controller.ep[0].ep, &ci_ep_init[0], sizeof(*ci_ep_init));
|
|
controller.ep[0].desc = &ep0_desc;
|
|
INIT_LIST_HEAD(&controller.ep[0].queue);
|
|
controller.ep[0].req_primed = false;
|
|
controller.gadget.ep0 = &controller.ep[0].ep;
|
|
INIT_LIST_HEAD(&controller.gadget.ep0->ep_list);
|
|
|
|
/* Init EP 1..n */
|
|
for (i = 1; i < NUM_ENDPOINTS; i++) {
|
|
memcpy(&controller.ep[i].ep, &ci_ep_init[1],
|
|
sizeof(*ci_ep_init));
|
|
INIT_LIST_HEAD(&controller.ep[i].queue);
|
|
controller.ep[i].req_primed = false;
|
|
list_add_tail(&controller.ep[i].ep.ep_list,
|
|
&controller.gadget.ep_list);
|
|
}
|
|
|
|
ci_ep_alloc_request(&controller.ep[0].ep, 0);
|
|
if (!controller.ep0_req) {
|
|
free(controller.items_mem);
|
|
free(controller.epts);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int usb_gadget_register_driver(struct usb_gadget_driver *driver)
|
|
{
|
|
int ret;
|
|
|
|
if (!driver)
|
|
return -EINVAL;
|
|
if (!driver->bind || !driver->setup || !driver->disconnect)
|
|
return -EINVAL;
|
|
if (driver->speed != USB_SPEED_FULL && driver->speed != USB_SPEED_HIGH)
|
|
return -EINVAL;
|
|
|
|
ret = usb_lowlevel_init(0, USB_INIT_DEVICE, (void **)&controller.ctrl);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ci_udc_probe();
|
|
#if defined(CONFIG_USB_EHCI_MX6) || defined(CONFIG_USB_EHCI_MXS)
|
|
/*
|
|
* FIXME: usb_lowlevel_init()->ehci_hcd_init() should be doing all
|
|
* HW-specific initialization, e.g. ULPI-vs-UTMI PHY selection
|
|
*/
|
|
if (!ret) {
|
|
struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
|
|
|
|
/* select ULPI phy */
|
|
writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc);
|
|
}
|
|
#endif
|
|
|
|
ret = driver->bind(&controller.gadget);
|
|
if (ret) {
|
|
DBG("driver->bind() returned %d\n", ret);
|
|
return ret;
|
|
}
|
|
controller.driver = driver;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
|
|
{
|
|
udc_disconnect();
|
|
|
|
driver->unbind(&controller.gadget);
|
|
controller.driver = NULL;
|
|
|
|
ci_ep_free_request(&controller.ep[0].ep, &controller.ep0_req->req);
|
|
free(controller.items_mem);
|
|
free(controller.epts);
|
|
|
|
return 0;
|
|
}
|
|
|
|
bool dfu_usb_get_reset(void)
|
|
{
|
|
struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
|
|
|
|
return !!(readl(&udc->usbsts) & STS_URI);
|
|
}
|