mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-22 02:49:44 +09:00
34fa07063a
these variables are curently defined in several config files but the driver doesn't use them and defaults to hardcoded values in nand_defs.h It's interesting to be able to change this hardcoded valude when the hardware is not using the default adress signals to drive ALE and CLE and two configuration defines already exist for this purpose so use them. Signed-off-by: Eric Bénard <eric@eukrea.com>
464 lines
14 KiB
C
464 lines
14 KiB
C
/*
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* (C) Copyright 2011
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* Based on:
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* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Based on davinci_dvevm.h. Original Copyrights follow:
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*
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* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* Board
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*/
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#define CONFIG_DRIVER_TI_EMAC
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#define CONFIG_SYS_DAVINCI_EMAC_PHY_COUNT 7
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#define CONFIG_USE_NAND
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/*
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* SoC Configuration
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*/
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#define CONFIG_ARM926EJS /* arm926ejs CPU core */
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#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
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#define CONFIG_SOC_DA850 /* TI DA850 SoC */
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#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
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#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
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#define CONFIG_SYS_OSCIN_FREQ 24000000
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#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
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#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
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#define CONFIG_SYS_HZ 1000
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#define CONFIG_DA850_LOWLEVEL
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#define CONFIG_ARCH_CPU_INIT
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#define CONFIG_SYS_DA850_PLL_INIT
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#define CONFIG_SYS_DA850_DDR_INIT
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#define CONFIG_DA8XX_GPIO
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#define CONFIG_HOSTNAME enbw_cmc
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#define MACH_TYPE_ENBW_CMC 3585
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#define CONFIG_MACH_TYPE MACH_TYPE_ENBW_CMC
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/*
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* Memory Info
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*/
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#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
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#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
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#define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */
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#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
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/* memtest start addr */
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#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
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/* memtest will be run on 16MB */
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#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_1 + 0x2000000 + 16*1024*1024)
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#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
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/*
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* Serial Driver info
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*/
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#define CONFIG_SYS_NS16550
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
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#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
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#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
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#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
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#define CONFIG_BAUDRATE 115200 /* Default baud rate */
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/*
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* I2C Configuration
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*/
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#define CONFIG_HARD_I2C
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#define CONFIG_DRIVER_DAVINCI_I2C
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#define CONFIG_SYS_I2C_SPEED 80000
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#define CONFIG_SYS_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */
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#define CONFIG_SYS_I2C_EXPANDER_ADDR 0x20
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_DTT
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#define CONFIG_DTT_LM75
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#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
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#define CONFIG_SYS_DTT_MAX_TEMP 70
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#define CONFIG_SYS_DTT_LOW_TEMP -30
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#define CONFIG_SYS_DTT_HYSTERESIS 3
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/*
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* SPI Configuration
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*/
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#define CONFIG_DAVINCI_SPI
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#define CONFIG_SYS_SPI_BASE DAVINCI_SPI1_BASE
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#define CONFIG_SYS_SPI_CLK clk_get(DAVINCI_SPI1_CLKID)
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#define CONFIG_CMD_SPI
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/*
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* Flash & Environment
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*/
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#ifdef CONFIG_USE_NAND
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#define CONFIG_NAND_DAVINCI
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#define CONFIG_SYS_NAND_USE_FLASH_BBT
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#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
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#define CONFIG_SYS_NAND_PAGE_2K
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#define CONFIG_SYS_NAND_CS 3
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#define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE
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#define CONFIG_SYS_NAND_MASK_CLE 0x10
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#define CONFIG_SYS_NAND_MASK_ALE 0x8
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#undef CONFIG_SYS_NAND_HW_ECC
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#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
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#define MTDIDS_DEFAULT "nor0=physmap-flash.0,nand0=davinci_nand.1"
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#define MTDPARTS_DEFAULT \
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"mtdparts=" \
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"physmap-flash.0:" \
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"512k(U-Boot)," \
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"64k(env1)," \
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"64k(env2)," \
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"-(rest);" \
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"davinci_nand.1:" \
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"128k(dtb)," \
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"3m(kernel)," \
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"4m(rootfs)," \
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"-(userfs)"
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#define CONFIG_CMD_MTDPARTS
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#endif
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/*
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* Network & Ethernet Configuration
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*/
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#ifdef CONFIG_DRIVER_TI_EMAC
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#define CONFIG_MII
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#define CONFIG_BOOTP_DEFAULT
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_DNS2
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#define CONFIG_NET_RETRY_COUNT 10
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#endif
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/*
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* Flash configuration
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*/
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_FLASH_CFI_MTD
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#define CONFIG_SYS_FLASH_BASE 0x60000000
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#define CONFIG_SYS_FLASH_SIZE 0x01000000
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#define CONFIG_SYS_MAX_FLASH_SECT 128
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#define CONFIG_FLASH_16BIT /* Flash is 16-bit */
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#define CONFIG_CMD_FLASH
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_SYS_MONITOR_LEN 0x80000
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
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CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SECT_SIZE (64 << 10)
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#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
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CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
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#undef CONFIG_ENV_IS_IN_NAND
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#define CONFIG_DEFAULT_SETTINGS_ADDR (CONFIG_ENV_ADDR_REDUND + \
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CONFIG_ENV_SECT_SIZE)
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"u-boot_addr_r=c0000000\0" \
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"u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
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"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
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"update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"\
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"erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
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"cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \
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" ${filesize};" \
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"protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\
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"netdev=eth0\0" \
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"rootpath=/opt/eldk-arm/arm\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=${serverip}:${rootpath}\0" \
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"ramargs=setenv bootargs root=/dev/ram rw\0" \
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"addip=setenv bootargs ${bootargs} " \
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"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
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":${hostname}:${netdev}:off panic=1\0" \
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"kernel_addr_r=c0700000\0" \
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"fdt_addr_r=c0600000\0" \
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"ramdisk_addr_r=c0b00000\0" \
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"fdt_file=" __stringify(CONFIG_HOSTNAME) "/" \
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__stringify(CONFIG_HOSTNAME) ".dtb\0" \
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"kernel_file=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \
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"nand_ld_ramdsk=nand read ${ramdisk_addr_r} 320000 400000\0" \
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"nand_ld_kernel=nand read ${kernel_addr_r} 20000 300000\0" \
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"nand_ld_fdt=nand read ${fdt_addr_r} 0 2000\0" \
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"load_kernel=tftp ${kernel_addr_r} ${kernel_file}\0" \
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"load_fdt=tftp ${fdt_addr_r} ${fdt_file}\0" \
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"load_nand=run nand_ld_ramdsk nand_ld_kernel nand_ld_fdt\0" \
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"addcon=setenv bootargs ${bootargs} console=ttyS2," \
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"${baudrate}n8\0" \
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"net_nfs=run load_fdt load_kernel; " \
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"run nfsargs addip addcon addmtd addmisc;" \
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"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
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"nand_selfnand=run load_nand ramargs addip addcon addmisc;bootm "\
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"${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
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"bootcmd=run net_nfs\0" \
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"machid=e01\0" \
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"key_cmd_0=echo key: 0\0" \
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"key_cmd_1=echo key: 1\0" \
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"key_cmd_2=echo key: 2\0" \
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"key_cmd_3=echo key: 3\0" \
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"key_magic_0=0\0" \
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"key_magic_1=1\0" \
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"key_magic_2=2\0" \
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"key_magic_3=3\0" \
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"magic_keys=0123\0" \
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"hwconfig=switch:lan=on,pwl=off,config=0x60100000\0" \
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"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
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"addmisc=setenv bootargs ${bootargs}\0" \
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"mtdids=" MTDIDS_DEFAULT "\0" \
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"mtdparts=" MTDPARTS_DEFAULT "\0" \
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"logversion=2\0" \
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"\0"
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/*
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* U-Boot general configuration
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*/
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#define CONFIG_BOOTFILE "uImage" /* Boot file name */
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#define CONFIG_SYS_PROMPT "=> " /* Command Prompt */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
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#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
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#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
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#define CONFIG_VERSION_VARIABLE
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_HUSH_PARSER
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#define CONFIG_CMDLINE_EDITING
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CRC32_VERIFY
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#define CONFIG_MX_CYCLIC
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#define CONFIG_BOOTDELAY 3
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#define CONFIG_HWCONFIG
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#define CONFIG_SHOW_BOOT_PROGRESS
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#define CONFIG_BOARD_LATE_INIT
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/*
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* U-Boot commands
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ENV
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_SAVES
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_CACHE
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#ifdef CONFIG_CMD_BDI
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#define CONFIG_CLOCKS
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#endif
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#ifndef CONFIG_DRIVER_TI_EMAC
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#undef CONFIG_CMD_NET
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#undef CONFIG_CMD_DHCP
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#undef CONFIG_CMD_MII
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#undef CONFIG_CMD_PING
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#endif
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#ifdef CONFIG_USE_NAND
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#undef CONFIG_CMD_IMLS
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_MTD_DEVICE
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#define CONFIG_MTD_PARTITIONS
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#define CONFIG_LZO
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#define CONFIG_RBTREE
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#define CONFIG_CMD_UBI
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#define CONFIG_CMD_UBIFS
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#endif
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#if !defined(CONFIG_USE_NAND) && \
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!defined(CONFIG_USE_NOR) && \
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!defined(CONFIG_USE_SPIFLASH)
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#define CONFIG_ENV_IS_NOWHERE
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#define CONFIG_SYS_NO_FLASH
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#define CONFIG_ENV_SIZE (16 << 10)
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#undef CONFIG_CMD_IMLS
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#undef CONFIG_CMD_ENV
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#endif
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#define CONFIG_SYS_TEXT_BASE 0x60000000
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#define CONFIG_SYS_SDRAM_BASE 0xc0000000
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#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00)
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#define CONFIG_VERSION_VARIABLE
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_PREBOOT "echo;" \
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"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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"echo"
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#define CONFIG_MISC_INIT_R
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#define CONFIG_CMC_RESET_PIN 0x04000000
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#define CONFIG_CMC_RESET_TIMEOUT 3
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#define CONFIG_HW_WATCHDOG
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#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
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#define CONFIG_SYS_WDT_PERIOD_LOW 0x0c000000
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#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0
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#define CONFIG_CMD_DATE
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#define CONFIG_RTC_DAVINCI
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/* SD/MMC */
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#define CONFIG_MMC
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#define CONFIG_GENERIC_MMC
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#define CONFIG_DAVINCI_MMC
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#define CONFIG_MMC_MBLOCK
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#define CONFIG_DOS_PARTITION
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_MMC
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/* GPIO */
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#define CONFIG_ENBW_CMC_BOARD_TYPE 57
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#define CONFIG_ENBW_CMC_HW_ID_BIT0 39
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#define CONFIG_ENBW_CMC_HW_ID_BIT1 38
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#define CONFIG_ENBW_CMC_HW_ID_BIT2 35
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/* FDT support */
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#define CONFIG_OF_LIBFDT
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/* LowLevel Init */
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/* PLL */
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#define CONFIG_SYS_DV_CLKMODE 0
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#define CONFIG_SYS_DA850_PLL0_POSTDIV 0
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#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
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#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
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#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002 /* 150MHz */
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#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
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#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
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#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
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#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
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#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
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#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
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#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
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#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
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#define CONFIG_SYS_DA850_PLL0_PLLM 18 /* PLL0 -> 456 MHz */
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#define CONFIG_SYS_DA850_PLL1_PLLM 24 /* PLL1 -> 300 MHz */
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/* DDR RAM */
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#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
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DV_DDR_PHY_EXT_STRBEN | \
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(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
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#define CONFIG_SYS_DA850_DDR2_SDBCR (0 | \
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(0 << DV_DDR_SDCR_DDR2TERM1_SHIFT) | \
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(0 << DV_DDR_SDCR_MSDRAMEN_SHIFT) | \
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(1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
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(0x1 << DV_DDR_SDCR_DDREN_SHIFT) | \
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(0x1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
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(0x1 << DV_DDR_SDCR_TIMUNLOCK_SHIFT) | \
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(0x1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
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(0x3 << DV_DDR_SDCR_CL_SHIFT) | \
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(0x2 << DV_DDR_SDCR_IBANK_SHIFT) | \
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(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
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#define CONFIG_SYS_DA850_DDR2_SDBCR2 4 /* 13 row address bits */
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/*
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* freq = 150MHz -> t = 7ns
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*/
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#define CONFIG_SYS_DA850_DDR2_SDTIMR (0 | \
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(0x0d << DV_DDR_SDTMR1_RFC_SHIFT) | \
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(1 << DV_DDR_SDTMR1_RP_SHIFT) | \
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(1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
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(1 << DV_DDR_SDTMR1_WR_SHIFT) | \
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(5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
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(7 << DV_DDR_SDTMR1_RC_SHIFT) | \
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(1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
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(readl(&dv_ddr2_regs_ctrl->sdtimr) & 0x4) | /* Reserved */ \
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((2 - 1) << DV_DDR_SDTMR1_WTR_SHIFT))
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/*
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* freq = 150MHz -> t=7ns
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*/
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#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (0 | \
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(readl(&dv_ddr2_regs_ctrl->sdtimr2) & 0x80000000) | /* Reserved */ \
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(8 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
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(2 << DV_DDR_SDTMR2_XP_SHIFT) | \
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(0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
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(15 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
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(27 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
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(0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
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(2 << DV_DDR_SDTMR2_CKE_SHIFT))
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#define CONFIG_SYS_DA850_DDR2_SDRCR 0x00000407
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#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
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#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
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DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
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DAVINCI_SYSCFG_SUSPSRC_UART2 | \
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DAVINCI_SYSCFG_SUSPSRC_EMAC |\
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DAVINCI_SYSCFG_SUSPSRC_I2C)
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#define CONFIG_SYS_DA850_CS2CFG (DAVINCI_ABCR_WSETUP(2) | \
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DAVINCI_ABCR_WSTROBE(6) | \
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DAVINCI_ABCR_WHOLD(1) | \
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DAVINCI_ABCR_RSETUP(2) | \
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DAVINCI_ABCR_RSTROBE(6) | \
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DAVINCI_ABCR_RHOLD(1) | \
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DAVINCI_ABCR_ASIZE_16BIT)
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#define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \
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DAVINCI_ABCR_WSTROBE(2) | \
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DAVINCI_ABCR_WHOLD(1) | \
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DAVINCI_ABCR_RSETUP(1) | \
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DAVINCI_ABCR_RSTROBE(6) | \
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DAVINCI_ABCR_RHOLD(1) | \
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DAVINCI_ABCR_ASIZE_8BIT)
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/*
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* NOR Bootconfiguration word:
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* Method: Direc boot
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* EMIFA access mode: 16 Bit
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*/
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#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
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#define CONFIG_POST (CONFIG_SYS_POST_MEMORY)
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#define CONFIG_POST_EXTERNAL_WORD_FUNCS
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#define CONFIG_SYS_POST_WORD_ADDR DAVINCI_RTC_BASE
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#define CONFIG_LOGBUFFER
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#define CONFIG_SYS_CONSOLE_IS_IN_ENV
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#define CONFIG_BOOTCOUNT_LIMIT
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#define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE
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#define CONFIG_SYS_BOOTCOUNT_BE
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#define CONFIG_SYS_NAND_U_BOOT_DST 0xc0080000
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#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x60004000
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#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x70000
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#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
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#endif /* __CONFIG_H */
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