mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 01:48:52 +09:00
237 lines
5.7 KiB
C
237 lines
5.7 KiB
C
/*
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* (C) Copyright 2002
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* Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/arch/pxa-regs.h>
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ------------------------------------------------------------------------- */
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/* local prototypes */
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void set_led (int led, int color);
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void error_code_halt (int code);
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int init_sio (int led, unsigned long base);
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inline void cradle_outb (unsigned short val, unsigned long base,
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unsigned long reg);
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inline unsigned char cradle_inb (unsigned long base, unsigned long reg);
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inline void sleep (int i);
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inline void
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/**********************************************************/
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sleep (int i)
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/**********************************************************/
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{
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while (i--) {
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udelay (1000000);
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}
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}
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void
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/**********************************************************/
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error_code_halt (int code)
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/**********************************************************/
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{
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while (1) {
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led_code (code, RED);
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sleep (1);
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led_code (0, OFF);
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sleep (1);
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}
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}
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void
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/**********************************************************/
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led_code (int code, int color)
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/**********************************************************/
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{
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int i;
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code &= 0xf; /* only 4 leds */
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for (i = 0; i < 4; i++) {
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if (code & (1 << i)) {
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set_led (i, color);
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} else {
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set_led (i, OFF);
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}
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}
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}
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void
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/**********************************************************/
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set_led (int led, int color)
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/**********************************************************/
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{
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int shift = led * 2;
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unsigned long mask = 0x3 << shift;
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writel(mask, GPCR2); /* clear bits */
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writel((color << shift), GPSR2); /* set bits */
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udelay (5000);
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}
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inline void
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/**********************************************************/
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cradle_outb (unsigned short val, unsigned long base, unsigned long reg)
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/**********************************************************/
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{
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*(volatile unsigned short *) (base + (reg * 2)) = val;
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}
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inline unsigned char
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/**********************************************************/
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cradle_inb (unsigned long base, unsigned long reg)
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/**********************************************************/
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{
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unsigned short val;
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val = *(volatile unsigned short *) (base + (reg * 2));
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return (val & 0xff);
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}
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int
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/**********************************************************/
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init_sio (int led, unsigned long base)
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/**********************************************************/
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{
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unsigned char val;
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set_led (led, YELLOW);
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val = cradle_inb (base, CRADLE_SIO_INDEX);
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val = cradle_inb (base, CRADLE_SIO_INDEX);
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if (val != 0) {
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set_led (led, RED);
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return -1;
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}
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/* map SCC2 to COM1 */
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cradle_outb (0x01, base, CRADLE_SIO_INDEX);
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cradle_outb (0x00, base, CRADLE_SIO_DATA);
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/* enable SCC2 extended regs */
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cradle_outb (0x40, base, CRADLE_SIO_INDEX);
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cradle_outb (0xa0, base, CRADLE_SIO_DATA);
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/* enable SCC2 clock multiplier */
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cradle_outb (0x51, base, CRADLE_SIO_INDEX);
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cradle_outb (0x04, base, CRADLE_SIO_DATA);
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/* enable SCC2 */
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cradle_outb (0x00, base, CRADLE_SIO_INDEX);
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cradle_outb (0x04, base, CRADLE_SIO_DATA);
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/* map SCC2 DMA to channel 0 */
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cradle_outb (0x4f, base, CRADLE_SIO_INDEX);
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cradle_outb (0x09, base, CRADLE_SIO_DATA);
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/* read ID from SIO to check operation */
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cradle_outb (0xe4, base, 0x3f8 + 0x3);
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val = cradle_inb (base, 0x3f8 + 0x0);
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if ((val & 0xf0) != 0x20) {
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set_led (led, RED);
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/* disable SCC2 */
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cradle_outb (0, base, CRADLE_SIO_INDEX);
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cradle_outb (0, base, CRADLE_SIO_DATA);
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return -1;
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}
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/* set back to bank 0 */
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cradle_outb (0, base, 0x3f8 + 0x3);
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set_led (led, GREEN);
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return 0;
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}
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/*
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* Miscelaneous platform dependent initialisations
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*/
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int
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/**********************************************************/
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board_late_init (void)
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/**********************************************************/
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{
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return (0);
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}
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int
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/**********************************************************/
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board_init (void)
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/**********************************************************/
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{
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/* We have RAM, disable cache */
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dcache_disable();
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icache_disable();
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led_code (0xf, YELLOW);
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/* arch number of HHP Cradle */
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gd->bd->bi_arch_number = MACH_TYPE_HHP_CRADLE;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = 0xa0000100;
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/* Init SIOs to enable SCC2 */
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udelay (100000); /* delay makes it look neat */
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init_sio (0, CRADLE_SIO1_PHYS);
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udelay (100000);
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init_sio (1, CRADLE_SIO2_PHYS);
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udelay (100000);
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init_sio (2, CRADLE_SIO3_PHYS);
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udelay (100000);
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set_led (3, GREEN);
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return 1;
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}
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extern void pxa_dram_init(void);
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int dram_init(void)
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{
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pxa_dram_init();
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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}
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC91111
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rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
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#endif
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return rc;
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}
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#endif
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