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44cdb5b6a1
The BRDCFG5[SPISDHC] register field of Qixis device is used
to control SPI and SDHC signal routing.
10 = Force SDHC Mode
- SPI_CS[0] is routed to CPLD for SDHC_VS use.
- SPI_CS[1] is unused.
- SPI_CS[2:3] are routed to the TDMRiser slot.
11 = Force eMMC Mode
- SPI_CS[0:3] are routed to the eMMC card.
0X = Auto Mode
- If SDHC_CS_B=0 (SDHC card installed): Use SDHC mode
described above.
- Else SDHC_CS_B=1 (no SDHC card installed): Use eMMC
mode described above.
In default the hardware uses auto mode, but sometimes we need
to use force SDHC mode to support SD card hotplug, or SD sleep
waking up in kernel. This patch is to support force SDHC mode
by hwconfig.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
46 lines
994 B
C
46 lines
994 B
C
/*
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __LS1088AQDS_QIXIS_H__
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#define __LS1088AQDS_QIXIS_H__
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/* Definitions of QIXIS Registers for LS1088AQDS */
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/* SYSCLK */
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#define QIXIS_SYSCLK_66 0x0
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#define QIXIS_SYSCLK_83 0x1
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#define QIXIS_SYSCLK_100 0x2
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#define QIXIS_SYSCLK_125 0x3
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#define QIXIS_SYSCLK_133 0x4
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#define QIXIS_SYSCLK_150 0x5
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#define QIXIS_SYSCLK_160 0x6
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#define QIXIS_SYSCLK_166 0x7
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/* DDRCLK */
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#define QIXIS_DDRCLK_66 0x0
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#define QIXIS_DDRCLK_100 0x1
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#define QIXIS_DDRCLK_125 0x2
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#define QIXIS_DDRCLK_133 0x3
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/* BRDCFG2 - SD clock*/
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#define QIXIS_SDCLK1_100 0x0
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#define QIXIS_SDCLK1_125 0x1
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#define QIXIS_SDCLK1_165 0x2
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#define QIXIS_SDCLK1_100_SP 0x3
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#define BRDCFG4_EMISEL_MASK 0xE0
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#define BRDCFG4_EMISEL_SHIFT 5
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#define BRDCFG9_SFPTX_MASK 0x10
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#define BRDCFG9_SFPTX_SHIFT 4
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/* Definitions of QIXIS Registers for LS1088ARDB */
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/* BRDCFG5 */
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#define BRDCFG5_SPISDHC_MASK 0x0C
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#define BRDCFG5_FORCE_SD 0x08
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#endif
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