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https://github.com/brain-hackers/u-boot-brain
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ad19e7a5d2
The old PCI ATMU setup code would just mimic the PCI regions into the ATMU registers. For simple memory maps in which all memory, MMIO, etc space fit into 4G this works ok. However there are issues with we have >4G of memory as we know can't access all of memory and we need to ensure that PCICSRBAR (PEXCSRBAR on PCIe) isn't overlapping with anything since we can't turn it off. We first setup outbound windows based on what the board code setup in the pci regions for MMIO and IO access. Next we place PCICSRBAR below the MMIO window. After which we try to setup the inbound windows to map as much of memory as possible. On PCIe based controllers we are able to overmap the ATMU setup since RX & TX links are separate but report the proper amount of inbound address space to the region tracking to ensure there is no overlap. On PCI based controllers we use as many inbound windows as available to map as much of the memory as possible. Additionally we changed all the CCSR register access to use proper IO accessor functions. Also had to add CONFIG_SYS_CCSRBAR_PHYS to some 86xx platforms that didn't have it defined. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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| .. | ||
| fsl_pci_init.c | ||
| Makefile | ||
| pci_auto.c | ||
| pci_indirect.c | ||
| pci_ixp.c | ||
| pci_sh4.c | ||
| pci_sh7751.c | ||
| pci_sh7780.c | ||
| pci.c | ||
| tsi108_pci.c | ||
| w83c553f.c | ||