mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 19:26:16 +09:00
350b50eea3
Move arch/arm/cpu/armv7armada-xp/* -> arch/arm/mach-mvebu/* Since this platform will be extended to support other Marvell SoC's as well, lets rename it directly to mvebu. This will be used by the upcoming Armada 38x suport (A38x). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com> Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
62 lines
1.1 KiB
ArmAsm
62 lines
1.1 KiB
ArmAsm
/*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <linux/linkage.h>
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ENTRY(save_boot_params)
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b save_boot_params_ret
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ENDPROC(save_boot_params)
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/*
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* cache_inv - invalidate Cache line
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* r0 - dest
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*/
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.global cache_inv
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.type cache_inv, %function
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cache_inv:
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stmfd sp!, {r1-r12}
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mcr p15, 0, r0, c7, c6, 1
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ldmfd sp!, {r1-r12}
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bx lr
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/*
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* flush_l1_v6 - l1 cache clean invalidate
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* r0 - dest
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*/
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.global flush_l1_v6
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.type flush_l1_v6, %function
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flush_l1_v6:
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stmfd sp!, {r1-r12}
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mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */
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mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
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mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */
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ldmfd sp!, {r1-r12}
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bx lr
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/*
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* flush_l1_v7 - l1 cache clean invalidate
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* r0 - dest
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*/
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.global flush_l1_v7
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.type flush_l1_v7, %function
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flush_l1_v7:
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stmfd sp!, {r1-r12}
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dmb /* @data memory barrier */
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mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
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dsb /* @data sync barrier */
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ldmfd sp!, {r1-r12}
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bx lr
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