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![Philipp Tomsich](/assets/img/avatar_default.png)
To send a parametrized command to the PHY over MDIO, we should write the data first, the trigger the execution by the command register write. Fix the access pattern in our MDIO write routine. Apparently this doesn't really matter with the Realtek PHY on the Pine64, but other PHYs (which require more setup) will choke on the wrong order. [Andre: add commit message] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Jagan Teki <jagan@openedev.com>
787 lines
19 KiB
C
787 lines
19 KiB
C
/*
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* (C) Copyright 2016
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* Author: Amit Singh Tomar, amittomer25@gmail.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Ethernet driver for H3/A64/A83T based SoC's
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*
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* It is derived from the work done by
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* LABBE Corentin & Chen-Yu Tsai for Linux, THANKS!
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*
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*/
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <common.h>
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#include <dm.h>
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#include <fdt_support.h>
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#include <linux/err.h>
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#include <malloc.h>
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#include <miiphy.h>
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#include <net.h>
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#define MDIO_CMD_MII_BUSY BIT(0)
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#define MDIO_CMD_MII_WRITE BIT(1)
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#define MDIO_CMD_MII_PHY_REG_ADDR_MASK 0x000001f0
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#define MDIO_CMD_MII_PHY_REG_ADDR_SHIFT 4
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#define MDIO_CMD_MII_PHY_ADDR_MASK 0x0001f000
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#define MDIO_CMD_MII_PHY_ADDR_SHIFT 12
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#define CONFIG_TX_DESCR_NUM 32
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#define CONFIG_RX_DESCR_NUM 32
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#define CONFIG_ETH_BUFSIZE 2048 /* Note must be dma aligned */
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/*
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* The datasheet says that each descriptor can transfers up to 4096 bytes
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* But later, the register documentation reduces that value to 2048,
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* using 2048 cause strange behaviours and even BSP driver use 2047
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*/
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#define CONFIG_ETH_RXSIZE 2044 /* Note must fit in ETH_BUFSIZE */
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#define TX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_TX_DESCR_NUM)
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#define RX_TOTAL_BUFSIZE (CONFIG_ETH_BUFSIZE * CONFIG_RX_DESCR_NUM)
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#define H3_EPHY_DEFAULT_VALUE 0x58000
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#define H3_EPHY_DEFAULT_MASK GENMASK(31, 15)
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#define H3_EPHY_ADDR_SHIFT 20
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#define REG_PHY_ADDR_MASK GENMASK(4, 0)
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#define H3_EPHY_LED_POL BIT(17) /* 1: active low, 0: active high */
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#define H3_EPHY_SHUTDOWN BIT(16) /* 1: shutdown, 0: power up */
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#define H3_EPHY_SELECT BIT(15) /* 1: internal PHY, 0: external PHY */
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#define SC_RMII_EN BIT(13)
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#define SC_EPIT BIT(2) /* 1: RGMII, 0: MII */
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#define SC_ETCS_MASK GENMASK(1, 0)
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#define SC_ETCS_EXT_GMII 0x1
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#define SC_ETCS_INT_GMII 0x2
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#define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ)
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#define AHB_GATE_OFFSET_EPHY 0
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#if defined(CONFIG_MACH_SUN8I_H3)
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#define SUN8I_GPD8_GMAC 2
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#else
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#define SUN8I_GPD8_GMAC 4
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#endif
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/* H3/A64 EMAC Register's offset */
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#define EMAC_CTL0 0x00
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#define EMAC_CTL1 0x04
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#define EMAC_INT_STA 0x08
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#define EMAC_INT_EN 0x0c
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#define EMAC_TX_CTL0 0x10
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#define EMAC_TX_CTL1 0x14
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#define EMAC_TX_FLOW_CTL 0x1c
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#define EMAC_TX_DMA_DESC 0x20
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#define EMAC_RX_CTL0 0x24
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#define EMAC_RX_CTL1 0x28
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#define EMAC_RX_DMA_DESC 0x34
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#define EMAC_MII_CMD 0x48
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#define EMAC_MII_DATA 0x4c
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#define EMAC_ADDR0_HIGH 0x50
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#define EMAC_ADDR0_LOW 0x54
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#define EMAC_TX_DMA_STA 0xb0
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#define EMAC_TX_CUR_DESC 0xb4
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#define EMAC_TX_CUR_BUF 0xb8
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#define EMAC_RX_DMA_STA 0xc0
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#define EMAC_RX_CUR_DESC 0xc4
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DECLARE_GLOBAL_DATA_PTR;
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enum emac_variant {
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A83T_EMAC = 1,
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H3_EMAC,
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A64_EMAC,
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};
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struct emac_dma_desc {
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u32 status;
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u32 st;
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u32 buf_addr;
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u32 next;
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} __aligned(ARCH_DMA_MINALIGN);
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struct emac_eth_dev {
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struct emac_dma_desc rx_chain[CONFIG_TX_DESCR_NUM];
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struct emac_dma_desc tx_chain[CONFIG_RX_DESCR_NUM];
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char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
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char txbuffer[TX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
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u32 interface;
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u32 phyaddr;
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u32 link;
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u32 speed;
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u32 duplex;
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u32 phy_configured;
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u32 tx_currdescnum;
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u32 rx_currdescnum;
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u32 addr;
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u32 tx_slot;
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bool use_internal_phy;
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enum emac_variant variant;
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void *mac_reg;
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phys_addr_t sysctl_reg;
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struct phy_device *phydev;
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struct mii_dev *bus;
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};
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static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
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{
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struct emac_eth_dev *priv = bus->priv;
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ulong start;
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u32 miiaddr = 0;
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int timeout = CONFIG_MDIO_TIMEOUT;
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miiaddr &= ~MDIO_CMD_MII_WRITE;
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miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
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miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
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MDIO_CMD_MII_PHY_REG_ADDR_MASK;
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miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
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miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
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MDIO_CMD_MII_PHY_ADDR_MASK;
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miiaddr |= MDIO_CMD_MII_BUSY;
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writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
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start = get_timer(0);
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while (get_timer(start) < timeout) {
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if (!(readl(priv->mac_reg + EMAC_MII_CMD) & MDIO_CMD_MII_BUSY))
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return readl(priv->mac_reg + EMAC_MII_DATA);
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udelay(10);
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};
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return -1;
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}
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static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
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u16 val)
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{
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struct emac_eth_dev *priv = bus->priv;
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ulong start;
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u32 miiaddr = 0;
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int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
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miiaddr &= ~MDIO_CMD_MII_PHY_REG_ADDR_MASK;
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miiaddr |= (reg << MDIO_CMD_MII_PHY_REG_ADDR_SHIFT) &
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MDIO_CMD_MII_PHY_REG_ADDR_MASK;
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miiaddr &= ~MDIO_CMD_MII_PHY_ADDR_MASK;
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miiaddr |= (addr << MDIO_CMD_MII_PHY_ADDR_SHIFT) &
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MDIO_CMD_MII_PHY_ADDR_MASK;
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miiaddr |= MDIO_CMD_MII_WRITE;
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miiaddr |= MDIO_CMD_MII_BUSY;
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writel(val, priv->mac_reg + EMAC_MII_DATA);
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writel(miiaddr, priv->mac_reg + EMAC_MII_CMD);
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start = get_timer(0);
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while (get_timer(start) < timeout) {
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if (!(readl(priv->mac_reg + EMAC_MII_CMD) &
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MDIO_CMD_MII_BUSY)) {
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ret = 0;
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break;
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}
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udelay(10);
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};
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return ret;
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}
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static int _sun8i_write_hwaddr(struct emac_eth_dev *priv, u8 *mac_id)
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{
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u32 macid_lo, macid_hi;
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macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
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(mac_id[3] << 24);
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macid_hi = mac_id[4] + (mac_id[5] << 8);
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writel(macid_hi, priv->mac_reg + EMAC_ADDR0_HIGH);
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writel(macid_lo, priv->mac_reg + EMAC_ADDR0_LOW);
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return 0;
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}
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static void sun8i_adjust_link(struct emac_eth_dev *priv,
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struct phy_device *phydev)
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{
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u32 v;
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v = readl(priv->mac_reg + EMAC_CTL0);
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if (phydev->duplex)
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v |= BIT(0);
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else
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v &= ~BIT(0);
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v &= ~0x0C;
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switch (phydev->speed) {
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case 1000:
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break;
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case 100:
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v |= BIT(2);
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v |= BIT(3);
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break;
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case 10:
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v |= BIT(3);
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break;
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}
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writel(v, priv->mac_reg + EMAC_CTL0);
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}
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static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg)
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{
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if (priv->use_internal_phy) {
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/* H3 based SoC's that has an Internal 100MBit PHY
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* needs to be configured and powered up before use
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*/
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*reg &= ~H3_EPHY_DEFAULT_MASK;
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*reg |= H3_EPHY_DEFAULT_VALUE;
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*reg |= priv->phyaddr << H3_EPHY_ADDR_SHIFT;
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*reg &= ~H3_EPHY_SHUTDOWN;
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*reg |= H3_EPHY_SELECT;
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} else
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/* This is to select External Gigabit PHY on
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* the boards with H3 SoC.
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*/
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*reg &= ~H3_EPHY_SELECT;
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return 0;
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}
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static int sun8i_emac_set_syscon(struct emac_eth_dev *priv)
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{
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int ret;
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u32 reg;
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reg = readl(priv->sysctl_reg);
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if (priv->variant == H3_EMAC) {
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ret = sun8i_emac_set_syscon_ephy(priv, ®);
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if (ret)
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return ret;
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}
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reg &= ~(SC_ETCS_MASK | SC_EPIT);
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if (priv->variant == H3_EMAC || priv->variant == A64_EMAC)
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reg &= ~SC_RMII_EN;
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switch (priv->interface) {
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case PHY_INTERFACE_MODE_MII:
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/* default */
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break;
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case PHY_INTERFACE_MODE_RGMII:
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reg |= SC_EPIT | SC_ETCS_INT_GMII;
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break;
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case PHY_INTERFACE_MODE_RMII:
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if (priv->variant == H3_EMAC ||
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priv->variant == A64_EMAC) {
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reg |= SC_RMII_EN | SC_ETCS_EXT_GMII;
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break;
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}
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/* RMII not supported on A83T */
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default:
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debug("%s: Invalid PHY interface\n", __func__);
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return -EINVAL;
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}
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writel(reg, priv->sysctl_reg);
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return 0;
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}
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static int sun8i_phy_init(struct emac_eth_dev *priv, void *dev)
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{
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struct phy_device *phydev;
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phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
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if (!phydev)
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return -ENODEV;
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phy_connect_dev(phydev, dev);
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priv->phydev = phydev;
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phy_config(priv->phydev);
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return 0;
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}
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static void rx_descs_init(struct emac_eth_dev *priv)
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{
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struct emac_dma_desc *desc_table_p = &priv->rx_chain[0];
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char *rxbuffs = &priv->rxbuffer[0];
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struct emac_dma_desc *desc_p;
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u32 idx;
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/* flush Rx buffers */
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flush_dcache_range((uintptr_t)rxbuffs, (ulong)rxbuffs +
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RX_TOTAL_BUFSIZE);
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for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
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desc_p = &desc_table_p[idx];
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desc_p->buf_addr = (uintptr_t)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]
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;
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desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
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desc_p->st |= CONFIG_ETH_RXSIZE;
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desc_p->status = BIT(31);
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}
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/* Correcting the last pointer of the chain */
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desc_p->next = (uintptr_t)&desc_table_p[0];
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flush_dcache_range((uintptr_t)priv->rx_chain,
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(uintptr_t)priv->rx_chain +
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sizeof(priv->rx_chain));
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writel((uintptr_t)&desc_table_p[0], (priv->mac_reg + EMAC_RX_DMA_DESC));
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priv->rx_currdescnum = 0;
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}
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static void tx_descs_init(struct emac_eth_dev *priv)
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{
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struct emac_dma_desc *desc_table_p = &priv->tx_chain[0];
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char *txbuffs = &priv->txbuffer[0];
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struct emac_dma_desc *desc_p;
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u32 idx;
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for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
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desc_p = &desc_table_p[idx];
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desc_p->buf_addr = (uintptr_t)&txbuffs[idx * CONFIG_ETH_BUFSIZE]
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;
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desc_p->next = (uintptr_t)&desc_table_p[idx + 1];
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desc_p->status = (1 << 31);
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desc_p->st = 0;
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}
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/* Correcting the last pointer of the chain */
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desc_p->next = (uintptr_t)&desc_table_p[0];
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/* Flush all Tx buffer descriptors */
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flush_dcache_range((uintptr_t)priv->tx_chain,
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(uintptr_t)priv->tx_chain +
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sizeof(priv->tx_chain));
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writel((uintptr_t)&desc_table_p[0], priv->mac_reg + EMAC_TX_DMA_DESC);
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priv->tx_currdescnum = 0;
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}
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static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr)
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{
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u32 reg, v;
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int timeout = 100;
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reg = readl((priv->mac_reg + EMAC_CTL1));
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if (!(reg & 0x1)) {
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/* Soft reset MAC */
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setbits_le32((priv->mac_reg + EMAC_CTL1), 0x1);
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do {
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reg = readl(priv->mac_reg + EMAC_CTL1);
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} while ((reg & 0x01) != 0 && (--timeout));
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if (!timeout) {
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printf("%s: Timeout\n", __func__);
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return -1;
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}
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}
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/* Rewrite mac address after reset */
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_sun8i_write_hwaddr(priv, enetaddr);
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v = readl(priv->mac_reg + EMAC_TX_CTL1);
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/* TX_MD Transmission starts after a full frame located in TX DMA FIFO*/
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v |= BIT(1);
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writel(v, priv->mac_reg + EMAC_TX_CTL1);
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v = readl(priv->mac_reg + EMAC_RX_CTL1);
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/* RX_MD RX DMA reads data from RX DMA FIFO to host memory after a
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* complete frame has been written to RX DMA FIFO
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*/
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v |= BIT(1);
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writel(v, priv->mac_reg + EMAC_RX_CTL1);
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/* DMA */
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writel(8 << 24, priv->mac_reg + EMAC_CTL1);
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/* Initialize rx/tx descriptors */
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rx_descs_init(priv);
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tx_descs_init(priv);
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/* PHY Start Up */
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genphy_parse_link(priv->phydev);
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sun8i_adjust_link(priv, priv->phydev);
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/* Start RX DMA */
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v = readl(priv->mac_reg + EMAC_RX_CTL1);
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v |= BIT(30);
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writel(v, priv->mac_reg + EMAC_RX_CTL1);
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/* Start TX DMA */
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v = readl(priv->mac_reg + EMAC_TX_CTL1);
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v |= BIT(30);
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writel(v, priv->mac_reg + EMAC_TX_CTL1);
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/* Enable RX/TX */
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setbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
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setbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
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return 0;
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}
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static int parse_phy_pins(struct udevice *dev)
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{
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int offset;
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const char *pin_name;
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int drive, pull, i;
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offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
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"pinctrl-0");
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if (offset < 0) {
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printf("WARNING: emac: cannot find pinctrl-0 node\n");
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return offset;
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}
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drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
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"allwinner,drive", 4);
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pull = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0,
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"allwinner,pull", 0);
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for (i = 0; ; i++) {
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int pin;
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pin_name = fdt_stringlist_get(gd->fdt_blob, offset,
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"allwinner,pins", i, NULL);
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if (!pin_name)
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break;
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if (pin_name[0] != 'P')
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continue;
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pin = (pin_name[1] - 'A') << 5;
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if (pin >= 26 << 5)
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continue;
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pin += simple_strtol(&pin_name[2], NULL, 10);
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sunxi_gpio_set_cfgpin(pin, SUN8I_GPD8_GMAC);
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sunxi_gpio_set_drv(pin, drive);
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sunxi_gpio_set_pull(pin, pull);
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}
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if (!i) {
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printf("WARNING: emac: cannot find allwinner,pins property\n");
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|
return -2;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int _sun8i_eth_recv(struct emac_eth_dev *priv, uchar **packetp)
|
|
{
|
|
u32 status, desc_num = priv->rx_currdescnum;
|
|
struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
|
|
int length = -EAGAIN;
|
|
int good_packet = 1;
|
|
uintptr_t desc_start = (uintptr_t)desc_p;
|
|
uintptr_t desc_end = desc_start +
|
|
roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
|
|
|
|
ulong data_start = (uintptr_t)desc_p->buf_addr;
|
|
ulong data_end;
|
|
|
|
/* Invalidate entire buffer descriptor */
|
|
invalidate_dcache_range(desc_start, desc_end);
|
|
|
|
status = desc_p->status;
|
|
|
|
/* Check for DMA own bit */
|
|
if (!(status & BIT(31))) {
|
|
length = (desc_p->status >> 16) & 0x3FFF;
|
|
|
|
if (length < 0x40) {
|
|
good_packet = 0;
|
|
debug("RX: Bad Packet (runt)\n");
|
|
}
|
|
|
|
data_end = data_start + length;
|
|
/* Invalidate received data */
|
|
invalidate_dcache_range(rounddown(data_start,
|
|
ARCH_DMA_MINALIGN),
|
|
roundup(data_end,
|
|
ARCH_DMA_MINALIGN));
|
|
if (good_packet) {
|
|
if (length > CONFIG_ETH_RXSIZE) {
|
|
printf("Received packet is too big (len=%d)\n",
|
|
length);
|
|
return -EMSGSIZE;
|
|
}
|
|
*packetp = (uchar *)(ulong)desc_p->buf_addr;
|
|
return length;
|
|
}
|
|
}
|
|
|
|
return length;
|
|
}
|
|
|
|
static int _sun8i_emac_eth_send(struct emac_eth_dev *priv, void *packet,
|
|
int len)
|
|
{
|
|
u32 v, desc_num = priv->tx_currdescnum;
|
|
struct emac_dma_desc *desc_p = &priv->tx_chain[desc_num];
|
|
uintptr_t desc_start = (uintptr_t)desc_p;
|
|
uintptr_t desc_end = desc_start +
|
|
roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
|
|
|
|
uintptr_t data_start = (uintptr_t)desc_p->buf_addr;
|
|
uintptr_t data_end = data_start +
|
|
roundup(len, ARCH_DMA_MINALIGN);
|
|
|
|
/* Invalidate entire buffer descriptor */
|
|
invalidate_dcache_range(desc_start, desc_end);
|
|
|
|
desc_p->st = len;
|
|
/* Mandatory undocumented bit */
|
|
desc_p->st |= BIT(24);
|
|
|
|
memcpy((void *)data_start, packet, len);
|
|
|
|
/* Flush data to be sent */
|
|
flush_dcache_range(data_start, data_end);
|
|
|
|
/* frame end */
|
|
desc_p->st |= BIT(30);
|
|
desc_p->st |= BIT(31);
|
|
|
|
/*frame begin */
|
|
desc_p->st |= BIT(29);
|
|
desc_p->status = BIT(31);
|
|
|
|
/*Descriptors st and status field has changed, so FLUSH it */
|
|
flush_dcache_range(desc_start, desc_end);
|
|
|
|
/* Move to next Descriptor and wrap around */
|
|
if (++desc_num >= CONFIG_TX_DESCR_NUM)
|
|
desc_num = 0;
|
|
priv->tx_currdescnum = desc_num;
|
|
|
|
/* Start the DMA */
|
|
v = readl(priv->mac_reg + EMAC_TX_CTL1);
|
|
v |= BIT(31);/* mandatory */
|
|
v |= BIT(30);/* mandatory */
|
|
writel(v, priv->mac_reg + EMAC_TX_CTL1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sun8i_eth_write_hwaddr(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
struct emac_eth_dev *priv = dev_get_priv(dev);
|
|
|
|
return _sun8i_write_hwaddr(priv, pdata->enetaddr);
|
|
}
|
|
|
|
static void sun8i_emac_board_setup(struct emac_eth_dev *priv)
|
|
{
|
|
struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
|
|
|
if (priv->use_internal_phy) {
|
|
/* Set clock gating for ephy */
|
|
setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY));
|
|
|
|
/* Deassert EPHY */
|
|
setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY));
|
|
}
|
|
|
|
/* Set clock gating for emac */
|
|
setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC));
|
|
|
|
/* De-assert EMAC */
|
|
setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC));
|
|
}
|
|
|
|
static int sun8i_mdio_init(const char *name, struct emac_eth_dev *priv)
|
|
{
|
|
struct mii_dev *bus = mdio_alloc();
|
|
|
|
if (!bus) {
|
|
debug("Failed to allocate MDIO bus\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
bus->read = sun8i_mdio_read;
|
|
bus->write = sun8i_mdio_write;
|
|
snprintf(bus->name, sizeof(bus->name), name);
|
|
bus->priv = (void *)priv;
|
|
|
|
return mdio_register(bus);
|
|
}
|
|
|
|
static int sun8i_emac_eth_start(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
|
|
return _sun8i_emac_eth_init(dev->priv, pdata->enetaddr);
|
|
}
|
|
|
|
static int sun8i_emac_eth_send(struct udevice *dev, void *packet, int length)
|
|
{
|
|
struct emac_eth_dev *priv = dev_get_priv(dev);
|
|
|
|
return _sun8i_emac_eth_send(priv, packet, length);
|
|
}
|
|
|
|
static int sun8i_emac_eth_recv(struct udevice *dev, int flags, uchar **packetp)
|
|
{
|
|
struct emac_eth_dev *priv = dev_get_priv(dev);
|
|
|
|
return _sun8i_eth_recv(priv, packetp);
|
|
}
|
|
|
|
static int _sun8i_free_pkt(struct emac_eth_dev *priv)
|
|
{
|
|
u32 desc_num = priv->rx_currdescnum;
|
|
struct emac_dma_desc *desc_p = &priv->rx_chain[desc_num];
|
|
uintptr_t desc_start = (uintptr_t)desc_p;
|
|
uintptr_t desc_end = desc_start +
|
|
roundup(sizeof(u32), ARCH_DMA_MINALIGN);
|
|
|
|
/* Make the current descriptor valid again */
|
|
desc_p->status |= BIT(31);
|
|
|
|
/* Flush Status field of descriptor */
|
|
flush_dcache_range(desc_start, desc_end);
|
|
|
|
/* Move to next desc and wrap-around condition. */
|
|
if (++desc_num >= CONFIG_RX_DESCR_NUM)
|
|
desc_num = 0;
|
|
priv->rx_currdescnum = desc_num;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sun8i_eth_free_pkt(struct udevice *dev, uchar *packet,
|
|
int length)
|
|
{
|
|
struct emac_eth_dev *priv = dev_get_priv(dev);
|
|
|
|
return _sun8i_free_pkt(priv);
|
|
}
|
|
|
|
static void sun8i_emac_eth_stop(struct udevice *dev)
|
|
{
|
|
struct emac_eth_dev *priv = dev_get_priv(dev);
|
|
|
|
/* Stop Rx/Tx transmitter */
|
|
clrbits_le32(priv->mac_reg + EMAC_RX_CTL0, BIT(31));
|
|
clrbits_le32(priv->mac_reg + EMAC_TX_CTL0, BIT(31));
|
|
|
|
/* Stop TX DMA */
|
|
clrbits_le32(priv->mac_reg + EMAC_TX_CTL1, BIT(30));
|
|
|
|
phy_shutdown(priv->phydev);
|
|
}
|
|
|
|
static int sun8i_emac_eth_probe(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
struct emac_eth_dev *priv = dev_get_priv(dev);
|
|
|
|
priv->mac_reg = (void *)pdata->iobase;
|
|
|
|
sun8i_emac_board_setup(priv);
|
|
sun8i_emac_set_syscon(priv);
|
|
|
|
sun8i_mdio_init(dev->name, priv);
|
|
priv->bus = miiphy_get_dev_by_name(dev->name);
|
|
|
|
return sun8i_phy_init(priv, dev);
|
|
}
|
|
|
|
static const struct eth_ops sun8i_emac_eth_ops = {
|
|
.start = sun8i_emac_eth_start,
|
|
.write_hwaddr = sun8i_eth_write_hwaddr,
|
|
.send = sun8i_emac_eth_send,
|
|
.recv = sun8i_emac_eth_recv,
|
|
.free_pkt = sun8i_eth_free_pkt,
|
|
.stop = sun8i_emac_eth_stop,
|
|
};
|
|
|
|
static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct eth_pdata *pdata = dev_get_platdata(dev);
|
|
struct emac_eth_dev *priv = dev_get_priv(dev);
|
|
const char *phy_mode;
|
|
int offset = 0;
|
|
|
|
pdata->iobase = dev_get_addr_name(dev, "emac");
|
|
priv->sysctl_reg = dev_get_addr_name(dev, "syscon");
|
|
|
|
pdata->phy_interface = -1;
|
|
priv->phyaddr = -1;
|
|
priv->use_internal_phy = false;
|
|
|
|
offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset,
|
|
"phy");
|
|
if (offset > 0)
|
|
priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg",
|
|
-1);
|
|
|
|
phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL);
|
|
|
|
if (phy_mode)
|
|
pdata->phy_interface = phy_get_interface_by_name(phy_mode);
|
|
printf("phy interface%d\n", pdata->phy_interface);
|
|
|
|
if (pdata->phy_interface == -1) {
|
|
debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
|
|
return -EINVAL;
|
|
}
|
|
|
|
priv->variant = dev_get_driver_data(dev);
|
|
|
|
if (!priv->variant) {
|
|
printf("%s: Missing variant '%s'\n", __func__,
|
|
(char *)priv->variant);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (priv->variant == H3_EMAC) {
|
|
if (fdt_getprop(gd->fdt_blob, dev->of_offset,
|
|
"allwinner,use-internal-phy", NULL))
|
|
priv->use_internal_phy = true;
|
|
}
|
|
|
|
priv->interface = pdata->phy_interface;
|
|
|
|
if (!priv->use_internal_phy)
|
|
parse_phy_pins(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id sun8i_emac_eth_ids[] = {
|
|
{.compatible = "allwinner,sun8i-h3-emac", .data = (uintptr_t)H3_EMAC },
|
|
{.compatible = "allwinner,sun50i-a64-emac",
|
|
.data = (uintptr_t)A64_EMAC },
|
|
{.compatible = "allwinner,sun8i-a83t-emac",
|
|
.data = (uintptr_t)A83T_EMAC },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(eth_sun8i_emac) = {
|
|
.name = "eth_sun8i_emac",
|
|
.id = UCLASS_ETH,
|
|
.of_match = sun8i_emac_eth_ids,
|
|
.ofdata_to_platdata = sun8i_emac_eth_ofdata_to_platdata,
|
|
.probe = sun8i_emac_eth_probe,
|
|
.ops = &sun8i_emac_eth_ops,
|
|
.priv_auto_alloc_size = sizeof(struct emac_eth_dev),
|
|
.platdata_auto_alloc_size = sizeof(struct eth_pdata),
|
|
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
|
};
|