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https://github.com/brain-hackers/u-boot-brain
synced 2024-09-13 00:03:26 +09:00
![Vikas Manocha](/assets/img/avatar_default.png)
This driver uses the same pin control binding as that of linux, binding document of this patch is copied from linux. One addition done is for GPIO input and output mode configuration which was missing. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
118 lines
2.9 KiB
C
118 lines
2.9 KiB
C
#include <common.h>
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#include <asm/arch/gpio.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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DECLARE_GLOBAL_DATA_PTR;
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static int prep_gpio_dsc(struct stm32_gpio_dsc *gpio_dsc, u32 port_pin)
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{
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gpio_dsc->port = (port_pin & 0xF000) >> 12;
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gpio_dsc->pin = (port_pin & 0x0F00) >> 8;
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debug("%s: GPIO:port= %d, pin= %d\n", __func__, gpio_dsc->port,
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gpio_dsc->pin);
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return 0;
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}
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static int prep_gpio_ctl(struct stm32_gpio_ctl *gpio_ctl, u32 gpio_fn, int node)
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{
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gpio_fn &= 0x00FF;
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switch (gpio_fn) {
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case 0:
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gpio_ctl->mode = STM32_GPIO_MODE_IN;
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break;
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case 1 ... 16:
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gpio_ctl->mode = STM32_GPIO_MODE_AF;
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gpio_ctl->af = gpio_fn - 1;
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break;
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case 17:
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gpio_ctl->mode = STM32_GPIO_MODE_AN;
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break;
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default:
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gpio_ctl->mode = STM32_GPIO_MODE_OUT;
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break;
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}
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gpio_ctl->speed = fdtdec_get_int(gd->fdt_blob, node, "slew-rate", 0);
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if (fdtdec_get_bool(gd->fdt_blob, node, "drive-open-drain"))
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gpio_ctl->otype = STM32_GPIO_OTYPE_OD;
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else
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gpio_ctl->otype = STM32_GPIO_OTYPE_PP;
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if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-up"))
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gpio_ctl->pupd = STM32_GPIO_PUPD_UP;
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else if (fdtdec_get_bool(gd->fdt_blob, node, "bias-pull-down"))
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gpio_ctl->pupd = STM32_GPIO_PUPD_DOWN;
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else
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gpio_ctl->pupd = STM32_GPIO_PUPD_NO;
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debug("%s: gpio fn= %d, slew-rate= %x, op type= %x, pull-upd is = %x\n",
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__func__, gpio_fn, gpio_ctl->speed, gpio_ctl->otype,
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gpio_ctl->pupd);
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return 0;
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}
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static int stm32_pinctrl_set_state_simple(struct udevice *dev,
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struct udevice *periph)
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{
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u32 pin_mux[50];
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struct fdtdec_phandle_args args;
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int rv, len;
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/* Get node pinctrl-0 */
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rv = fdtdec_parse_phandle_with_args(gd->fdt_blob, periph->of_offset,
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"pinctrl-0", 0, 0, 0, &args);
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if (rv)
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return rv;
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/*
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* check for "pinmux" property in each subnode (e.g. pins1 and pins2 for
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* usart1) of pin controller phandle "pinctrl-0"
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* */
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fdt_for_each_subnode(args.node, gd->fdt_blob, args.node) {
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struct stm32_gpio_dsc gpio_dsc;
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struct stm32_gpio_ctl gpio_ctl;
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int i;
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len = fdtdec_get_int_array_count(gd->fdt_blob, args.node,
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"pinmux", pin_mux,
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ARRAY_SIZE(pin_mux));
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debug("%s: periph->name = %s, no of pinmux entries= %d\n",
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__func__, periph->name, len);
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if (len < 0)
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return -EINVAL;
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for (i = 0; i < len; i++) {
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debug("%s: pinmux = %x\n", __func__, *(pin_mux + i));
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prep_gpio_dsc(&gpio_dsc, *(pin_mux + i));
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prep_gpio_ctl(&gpio_ctl, *(pin_mux + i), args.node);
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rv = stm32_gpio_config(&gpio_dsc, &gpio_ctl);
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debug("%s: rv = %d\n\n", __func__, rv);
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if (rv)
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return rv;
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}
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}
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return 0;
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}
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static struct pinctrl_ops stm32_pinctrl_ops = {
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.set_state_simple = stm32_pinctrl_set_state_simple,
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};
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static const struct udevice_id stm32_pinctrl_ids[] = {
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{ .compatible = "st,stm32f746-pinctrl" },
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{ }
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};
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U_BOOT_DRIVER(pinctrl_stm32) = {
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.name = "pinctrl_stm32",
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.id = UCLASS_PINCTRL,
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.of_match = stm32_pinctrl_ids,
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.ops = &stm32_pinctrl_ops,
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.bind = dm_scan_fdt_dev,
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};
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