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![]() The endpoint rx count register value will be zero if it is read before receive packet ready bit (PERI_RXCSR:RXPKTRDY) is set. Check for the receive packet ready bit (PERI_RXCSR:RXPKTRDY) before reading endpoint rx count register. Proceed with rx count read and FIFO read only if RXPKTRDY bit is set. Signed-off-by: Pankaj Bharadiya <pankaj.bharadiya@ti.com> Signed-off-by: Tom Rini <trini@ti.com> |
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.. | ||
am35x.c | ||
am35x.h | ||
blackfin_usb.c | ||
blackfin_usb.h | ||
da8xx.c | ||
davinci.c | ||
davinci.h | ||
Makefile | ||
musb_core.c | ||
musb_core.h | ||
musb_debug.h | ||
musb_hcd.c | ||
musb_hcd.h | ||
musb_udc.c | ||
omap3.c | ||
omap3.h |