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https://github.com/brain-hackers/u-boot-brain
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![Chris Zankel](/assets/img/avatar_default.png)
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
223 lines
6.3 KiB
C
223 lines
6.3 KiB
C
/*
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* (C) Copyright 2007 Tensilica, Inc.
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* (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _XTENSA_LDSCRIPT_H
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#define _XTENSA_LDSCRIPT_H
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/*
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* This linker script is pre-processed with CPP to avoid hard-coding
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* addresses that depend on the Xtensa core configuration, because
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* this FPGA board can be used with a huge variety of Xtensa cores.
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*/
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#include <asm/arch/core.h>
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#include <asm/addrspace.h>
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#define ALIGN_LMA 4
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#define LMA_EQ_VMA
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#define FORCE_OUTPUT . = .
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#define FOLLOWING(sec) \
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AT(((LOADADDR(sec) + SIZEOF(sec) + ALIGN_LMA-1)) & ~(ALIGN_LMA-1))
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/*
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* Specify an output section that will be added to the ROM store table
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* (PACKED_SECTION) or one that will be resident in ROM (RESIDENT_SECTION).
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* 'symname' is a base name for section boundary symbols *_start & *_end.
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* 'lma' is the load address at which a section will be packed in ROM.
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* 'region' is the basename identifying a memory region and program header.
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* 'keep' prevents removal of empty sections (must be 'KEEP' or 'NOKEEP').
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*/
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#define RELOCATE1(_sec_) \
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LONG(_##_sec_##_start); \
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LONG(_##_sec_##_end); \
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LONG(LOADADDR(.##_sec_));
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#define RELOCATE2(_sym_, _sec_) \
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LONG(_##_sym_##_##_sec_##_start); \
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LONG(_##_sym_##_##_sec_##_end); \
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LONG(LOADADDR(.##_sym_##.##_sec_));
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#define SECTION_VECTOR(_sym_, _sec_, _vma_, _lma_) \
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.##_sym_##.##_sec_ _vma_ : _lma_ \
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{ \
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. = ALIGN(4); \
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_##_sym_##_##_sec_##_start = ABSOLUTE(.); \
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KEEP(*(.##_sym_##.##_sec_)) \
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_##_sym_##_##_sec_##_end = ABSOLUTE(.); \
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}
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/* In MMU configs there are two aliases of SYSROM, cached and uncached.
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* For various reasons it is simpler to use the uncached mapping for load
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* addresses, so ROM sections end up contiguous with the reset vector and
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* we get a compact binary image. However we can gain performance by doing
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* the unpacking from the cached ROM mapping. So we adjust all the load
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* addresses in the ROM store table with an offset to the cached mapping,
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* including the symbols referring to the ROM store table itself.
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*/
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#define SECTION_ResetVector(_vma_, _lma_) \
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.ResetVector.text _vma_ : _lma_ \
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{ \
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FORCE_OUTPUT; \
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KEEP(*(.ResetVector.text)); \
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KEEP(*(.reset.literal .reset.text)) \
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}
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#define SECTION_text(_vma_, _lma_) \
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.text _vma_ : _lma_ \
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{ \
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_text_start = ABSOLUTE(.); \
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*(.literal .text) \
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*(.literal.* .text.* .stub) \
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*(.gnu.warning .gnu.linkonce.literal.*) \
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*(.gnu.linkonce.t.*.literal .gnu.linkonce.t.*) \
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*(.fini.literal) \
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*(.fini) \
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*(.gnu.version) \
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_text_end = ABSOLUTE(.); \
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}
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#define SECTION_rodata(_vma_, _lma_) \
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.rodata _vma_ : _lma_ \
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{ \
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_rodata_start = ABSOLUTE(.); \
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*(.rodata) \
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*(.rodata.*) \
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*(.dtb.init.rodata) \
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*(.gnu.linkonce.r.*) \
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*(.rodata1) \
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__XT_EXCEPTION_TABLE__ = ABSOLUTE(.); \
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*(.xt_except_table) \
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*(.gcc_except_table) \
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*(.gnu.linkonce.e.*) \
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*(.gnu.version_r) \
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. = ALIGN(16); \
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_rodata_end = ABSOLUTE(.); \
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}
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#define SECTION_u_boot_list(_vma_, _lma_) \
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.u_boot_list _vma_ : _lma_ \
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{ \
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_u_boot_list_start = ABSOLUTE(.); \
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KEEP(*(SORT(.u_boot_list*))); \
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_u_boot_list_end = ABSOLUTE(.); \
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}
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#define SECTION_data(_vma_, _lma_) \
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.data _vma_ : _lma_ \
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{ \
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_data_start = ABSOLUTE(.); \
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*(.data) \
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*(.data.*) \
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*(.gnu.linkonce.d.*) \
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*(.data1) \
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*(.sdata) \
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*(.sdata.*) \
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*(.gnu.linkonce.s.*) \
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*(.sdata2) \
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*(.sdata2.*) \
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*(.gnu.linkonce.s2.*) \
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*(.jcr) \
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*(.eh_frame) \
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*(.dynamic) \
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*(.gnu.version_d) \
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_data_end = ABSOLUTE(.); \
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}
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#define SECTION_lit4(_vma_, _lma_) \
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.lit4 _vma_ : _lma_ \
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{ \
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_lit4_start = ABSOLUTE(.); \
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*(*.lit4) \
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*(.gnu.linkonce.lit4.*) \
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_lit4_end = ABSOLUTE(.); \
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}
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#define SECTION_bss(_vma_, _lma_) \
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.bss _vma_ : _lma_ \
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{ \
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. = ALIGN(8); \
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_bss_start = ABSOLUTE(.); \
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__bss_start = ABSOLUTE(.); \
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*(.dynsbss) \
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*(.sbss) \
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*(.sbss.*) \
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*(.gnu.linkonce.sb.*) \
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*(.scommon) \
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*(.sbss2) \
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*(.sbss2.*) \
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*(.gnu.linkonce.sb2.*) \
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*(.dynbss) \
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*(.bss) \
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*(.bss.*) \
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*(.gnu.linkonce.b.*) \
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*(COMMON) \
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*(.sram.bss) \
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. = ALIGN(8); \
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_bss_end = ABSOLUTE(.); \
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__bss_end = ABSOLUTE(.); \
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_end = ALIGN(0x8); \
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PROVIDE(end = ALIGN(0x8)); \
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_stack_sentry = ALIGN(0x8); \
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}
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#define SECTION_debug \
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.debug 0 : { *(.debug) } \
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.line 0 : { *(.line) } \
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.debug_srcinfo 0 : { *(.debug_srcinfo) } \
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.debug_sfnames 0 : { *(.debug_sfnames) } \
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.debug_aranges 0 : { *(.debug_aranges) } \
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.debug_pubnames 0 : { *(.debug_pubnames) } \
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.debug_info 0 : { *(.debug_info) } \
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.debug_abbrev 0 : { *(.debug_abbrev) } \
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.debug_line 0 : { *(.debug_line) } \
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.debug_frame 0 : { *(.debug_frame) } \
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.debug_str 0 : { *(.debug_str) } \
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.debug_loc 0 : { *(.debug_loc) } \
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.debug_macinfo 0 : { *(.debug_macinfo) } \
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.debug_weaknames 0 : { *(.debug_weaknames) } \
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.debug_funcnames 0 : { *(.debug_funcnames) } \
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.debug_typenames 0 : { *(.debug_typenames) } \
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.debug_varnames 0 : { *(.debug_varnames) }
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#define SECTION_xtensa \
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.xt.insn 0 : \
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{ \
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KEEP (*(.xt.insn)) \
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KEEP (*(.gnu.linkonce.x.*)) \
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} \
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.xt.prop 0 : \
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{ \
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KEEP (*(.xt.prop)) \
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KEEP (*(.xt.prop.*)) \
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KEEP (*(.gnu.linkonce.prop.*)) \
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} \
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.xt.lit 0 : \
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{ \
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KEEP (*(.xt.lit)) \
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KEEP (*(.xt.lit.*)) \
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KEEP (*(.gnu.linkonce.p.*)) \
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} \
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.xt.profile_range 0 : \
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{ \
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KEEP (*(.xt.profile_range)) \
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KEEP (*(.gnu.linkonce.profile_range.*)) \
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} \
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.xt.profile_ranges 0 : \
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{ \
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KEEP (*(.xt.profile_ranges)) \
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KEEP (*(.gnu.linkonce.xt.profile_ranges.*)) \
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} \
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.xt.profile_files 0 : \
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{ \
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KEEP (*(.xt.profile_files)) \
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KEEP (*(.gnu.linkonce.xt.profile_files.*)) \
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}
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#endif /* _XTENSA_LDSCRIPT_H */
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