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![Chris Zankel](/assets/img/avatar_default.png)
The Xtensa processor architecture is a configurable, extensible, and synthesizable 32-bit RISC processor core provided by Tensilica, inc. This is the second part of the basic architecture port, adding the 'arch/xtensa' directory and a readme file. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
25 lines
480 B
C
25 lines
480 B
C
/*
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* Copyright (C) 2009 Tensilica Inc.
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* Copyright (C) 2014 - 2016 Cadence Design Systems Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_CONFIG_H_
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#define _ASM_CONFIG_H_
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#include <asm/arch/core.h>
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#define CONFIG_LMB
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/*
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* Make boot parameters available in the MMUv2 virtual memory layout by
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* restricting used physical memory to the first 128MB.
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*/
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#if XCHAL_HAVE_PTP_MMU
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_MAX_MEM_MAPPED (128 << 20)
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#endif
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#endif
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