Lei Wen abbbbdd7e1 armada100: define CONFIG_SYS_CACHELINE_SIZE ... By default, on Armada100 SoC DCache Lnd ICache line lengths are 32 bytes long Signed-off-by: Lei Wen <leiwen@marvell.com>		2011-11-03 22:56:22 +01:00
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armada100.h	ARM: armada100: reduce dependence of including platform file	2011-10-27 21:56:33 +02:00
config.h	armada100: define CONFIG_SYS_CACHELINE_SIZE	2011-11-03 22:56:22 +01:00
cpu.h	ARM: armada100: reduce dependence of including platform file	2011-10-27 21:56:33 +02:00
gpio.h	gpio: Add GPIO driver for Marvell SoC Armada100	2011-09-30 22:00:53 +02:00
mfp.h	Armada100: Add SPI support for Marvell gplugD	2011-10-27 21:56:32 +02:00
spi.h	SPI: Add SPI driver support for Marvell Armada100	2011-10-27 21:56:32 +02:00