Marek Vasut abb25f4e95 arm: socfpga: reset: Add function to reset FPGA bridges ... Add function to enable and disable FPGA bridges. This code is used by the FPGA manager to disable the bridges before programming the FPGA and will later be also used by the initialization code for the chip to put the chip into well defined state during startup. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Acked-by: Pavel Machek <pavel@denx.de>		2014-10-06 17:46:50 +02:00
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clock_manager.h	arm: socfpga: clock: Sync with reference code	2014-10-06 17:46:49 +02:00
dwmmc.h	socfpga/dwmmc: Adding DesignWare MMC driver support for SOCFPGA	2014-01-09 11:53:55 +02:00
fpga_manager.h	arm: socfpga: fpga: Add SoCFPGA FPGA programming interface	2014-10-06 17:46:50 +02:00
freeze_controller.h	socfpga: Adding Freeze Controller driver	2013-12-03 14:38:56 +01:00
reset_manager.h	arm: socfpga: reset: Add function to reset FPGA bridges	2014-10-06 17:46:50 +02:00
scan_manager.h	socfpga: Fix SOCFPGA build error for Altera dev kit	2014-08-29 15:50:54 -04:00
socfpga_base_addrs.h	arm: socfpga: Clean up base address file	2014-10-06 17:46:48 +02:00
spl.h	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00
system_manager.h	arm: socfpga: misc: Add proper ethernet initialization	2014-10-06 17:46:49 +02:00
timer.h	Add GPL-2.0+ SPDX-License-Identifier to source files	2013-07-24 09:44:38 -04:00