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![Bin Meng](/assets/img/avatar_default.png)
When a driver declares DM_FLAG_PRE_RELOC flag, it wishes to be bound before relocation. However due to a bug in the DM core, the flag only takes effect when devices are statically declared via U_BOOT_DEVICE(). This bug has been fixed recently by commit "dm: core: Respect drivers with the DM_FLAG_PRE_RELOC flag in lists_bind_fdt()", but with the fix, it has a side effect that all existing drivers that declared DM_FLAG_PRE_RELOC flag will be bound before relocation now. This may expose potential boot failure on some boards due to insufficient memory during the pre-relocation stage. To mitigate this potential impact, the following changes are implemented: - Remove DM_FLAG_PRE_RELOC flag in the driver, if the driver only supports configuration from device tree (OF_CONTROL) - Keep DM_FLAG_PRE_RELOC flag in the driver only if the device is statically declared via U_BOOT_DEVICE() - Surround DM_FLAG_PRE_RELOC flag with OF_CONTROL check, for drivers that support both statically declared devices and configuration from device tree Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
174 lines
3.6 KiB
C
174 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Stefan Roese <sr@denx.de>
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*/
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#include <common.h>
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#include <dm.h>
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#include <serial.h>
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#include <asm/io.h>
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struct mvebu_platdata {
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void __iomem *base;
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};
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/*
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* Register offset
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*/
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#define UART_RX_REG 0x00
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#define UART_TX_REG 0x04
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#define UART_CTRL_REG 0x08
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#define UART_STATUS_REG 0x0c
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#define UART_BAUD_REG 0x10
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#define UART_POSSR_REG 0x14
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#define UART_STATUS_RX_RDY 0x10
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#define UART_STATUS_TXFIFO_FULL 0x800
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#define UART_CTRL_RXFIFO_RESET 0x4000
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#define UART_CTRL_TXFIFO_RESET 0x8000
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#define CONFIG_UART_BASE_CLOCK 25804800
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static int mvebu_serial_putc(struct udevice *dev, const char ch)
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{
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struct mvebu_platdata *plat = dev_get_platdata(dev);
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void __iomem *base = plat->base;
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while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL)
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;
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writel(ch, base + UART_TX_REG);
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return 0;
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}
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static int mvebu_serial_getc(struct udevice *dev)
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{
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struct mvebu_platdata *plat = dev_get_platdata(dev);
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void __iomem *base = plat->base;
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while (!(readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY))
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;
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return readl(base + UART_RX_REG) & 0xff;
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}
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static int mvebu_serial_pending(struct udevice *dev, bool input)
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{
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struct mvebu_platdata *plat = dev_get_platdata(dev);
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void __iomem *base = plat->base;
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if (readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY)
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return 1;
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return 0;
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}
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static int mvebu_serial_setbrg(struct udevice *dev, int baudrate)
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{
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struct mvebu_platdata *plat = dev_get_platdata(dev);
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void __iomem *base = plat->base;
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/*
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* Calculate divider
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* baudrate = clock / 16 / divider
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*/
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writel(CONFIG_UART_BASE_CLOCK / baudrate / 16, base + UART_BAUD_REG);
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/*
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* Set Programmable Oversampling Stack to 0,
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* UART defaults to 16x scheme
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*/
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writel(0, base + UART_POSSR_REG);
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return 0;
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}
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static int mvebu_serial_probe(struct udevice *dev)
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{
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struct mvebu_platdata *plat = dev_get_platdata(dev);
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void __iomem *base = plat->base;
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/* reset FIFOs */
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writel(UART_CTRL_RXFIFO_RESET | UART_CTRL_TXFIFO_RESET,
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base + UART_CTRL_REG);
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/* No Parity, 1 Stop */
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writel(0, base + UART_CTRL_REG);
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return 0;
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}
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static int mvebu_serial_ofdata_to_platdata(struct udevice *dev)
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{
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struct mvebu_platdata *plat = dev_get_platdata(dev);
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plat->base = devfdt_get_addr_ptr(dev);
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return 0;
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}
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static const struct dm_serial_ops mvebu_serial_ops = {
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.putc = mvebu_serial_putc,
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.pending = mvebu_serial_pending,
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.getc = mvebu_serial_getc,
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.setbrg = mvebu_serial_setbrg,
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};
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static const struct udevice_id mvebu_serial_ids[] = {
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{ .compatible = "marvell,armada-3700-uart" },
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{ }
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};
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U_BOOT_DRIVER(serial_mvebu) = {
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.name = "serial_mvebu",
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.id = UCLASS_SERIAL,
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.of_match = mvebu_serial_ids,
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.ofdata_to_platdata = mvebu_serial_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct mvebu_platdata),
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.probe = mvebu_serial_probe,
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.ops = &mvebu_serial_ops,
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};
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#ifdef CONFIG_DEBUG_MVEBU_A3700_UART
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#include <debug_uart.h>
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static inline void _debug_uart_init(void)
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{
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void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
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/* reset FIFOs */
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writel(UART_CTRL_RXFIFO_RESET | UART_CTRL_TXFIFO_RESET,
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base + UART_CTRL_REG);
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/* No Parity, 1 Stop */
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writel(0, base + UART_CTRL_REG);
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/*
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* Calculate divider
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* baudrate = clock / 16 / divider
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*/
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writel(CONFIG_UART_BASE_CLOCK / 115200 / 16, base + UART_BAUD_REG);
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/*
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* Set Programmable Oversampling Stack to 0,
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* UART defaults to 16x scheme
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*/
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writel(0, base + UART_POSSR_REG);
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}
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static inline void _debug_uart_putc(int ch)
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{
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void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
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while (readl(base + UART_STATUS_REG) & UART_STATUS_TXFIFO_FULL)
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;
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writel(ch, base + UART_TX_REG);
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}
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DEBUG_UART_FUNCS
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#endif
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