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![Dirk Eibach](/assets/img/avatar_default.png)
A set of accessor functions was added to be able to access not only memory mapped FPGA in a generic way. Thanks to Wolfgang Denk for getting this sorted properly. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Stefan Roese <sr@denx.de>
215 lines
4.1 KiB
C
215 lines
4.1 KiB
C
/*
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* (C) Copyright 2010
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/ppc4xx-gpio.h>
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#include <dtt.h>
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#include <miiphy.h>
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#include "405ep.h"
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#include <gdsys_fpga.h>
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#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
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#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
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#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
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#define PHYREG_CONTROL 0
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#define PHYREG_PAGE_ADDRESS 22
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#define PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1 16
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#define PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2 26
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enum {
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UNITTYPE_CCD_SWITCH = 1,
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};
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enum {
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HWVER_100 = 0,
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HWVER_110 = 1,
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HWVER_121 = 2,
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HWVER_122 = 3,
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};
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struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
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int misc_init_r(void)
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{
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/* startup fans */
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dtt_init();
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return 0;
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}
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int configure_gbit_phy(unsigned char addr)
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{
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unsigned short value;
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/* select page 2 */
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if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
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PHYREG_PAGE_ADDRESS, 0x0002))
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goto err_out;
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/* disable SGMII autonegotiation */
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if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
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PHYREG_PG2_COPPER_SPECIFIC_CONTROL_2, 0x800a))
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goto err_out;
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/* select page 0 */
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if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
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PHYREG_PAGE_ADDRESS, 0x0000))
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goto err_out;
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/* switch from powerdown to normal operation */
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if (miiphy_read(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
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PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, &value))
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goto err_out;
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if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
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PHYREG_PG0_COPPER_SPECIFIC_CONTROL_1, value & ~0x0004))
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goto err_out;
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/* reset phy so settings take effect */
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if (miiphy_write(CONFIG_SYS_GBIT_MII_BUSNAME, addr,
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PHYREG_CONTROL, 0x9140))
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goto err_out;
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return 0;
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err_out:
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printf("Error writing to the PHY addr=%02x\n", addr);
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return -1;
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}
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/*
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* Check Board Identity:
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*/
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int checkboard(void)
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{
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char *s = getenv("serial#");
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puts("Board: CATCenter Io");
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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puts("\n");
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return 0;
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}
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static void print_fpga_info(void)
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{
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u16 versions;
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u16 fpga_version;
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u16 fpga_features;
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unsigned unit_type;
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unsigned hardware_version;
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unsigned feature_channels;
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unsigned feature_expansion;
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FPGA_GET_REG(0, versions, &versions);
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FPGA_GET_REG(0, fpga_version, &fpga_version);
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FPGA_GET_REG(0, fpga_features, &fpga_features);
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unit_type = (versions & 0xf000) >> 12;
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hardware_version = versions & 0x000f;
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feature_channels = fpga_features & 0x007f;
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feature_expansion = fpga_features & (1<<15);
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puts("FPGA: ");
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switch (unit_type) {
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case UNITTYPE_CCD_SWITCH:
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printf("CCD-Switch");
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break;
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default:
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printf("UnitType %d(not supported)", unit_type);
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break;
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}
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switch (hardware_version) {
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case HWVER_100:
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printf(" HW-Ver 1.00\n");
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break;
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case HWVER_110:
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printf(" HW-Ver 1.10\n");
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break;
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case HWVER_121:
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printf(" HW-Ver 1.21\n");
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break;
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case HWVER_122:
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printf(" HW-Ver 1.22\n");
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break;
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default:
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printf(" HW-Ver %d(not supported)\n",
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hardware_version);
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break;
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}
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printf(" FPGA V %d.%02d, features:",
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fpga_version / 100, fpga_version % 100);
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printf(" %d channel(s)", feature_channels);
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printf(", expansion %ssupported\n", feature_expansion ? "" : "un");
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}
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/*
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* setup Gbit PHYs
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*/
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int last_stage_init(void)
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{
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unsigned int k;
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print_fpga_info();
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miiphy_register(CONFIG_SYS_GBIT_MII_BUSNAME,
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bb_miiphy_read, bb_miiphy_write);
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for (k = 0; k < 32; ++k)
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configure_gbit_phy(k);
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/* take fpga serdes blocks out of reset */
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FPGA_SET_REG(0, quad_serdes_reset, 0);
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return 0;
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}
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void gd405ep_init(void)
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{
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}
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void gd405ep_set_fpga_reset(unsigned state)
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{
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if (state) {
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out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
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out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
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} else {
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out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
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out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
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}
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}
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void gd405ep_setup_hw(void)
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{
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/*
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* set "startup-finished"-gpios
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*/
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gpio_write_bit(21, 0);
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gpio_write_bit(22, 1);
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}
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int gd405ep_get_fpga_done(unsigned fpga)
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{
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return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
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}
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