mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-14 15:16:16 +09:00
ab86f72c35
Change the implementation for arm926 to relocate the code to an arbitrary address in RAM. Adapt the TX25 (i.MX25), magnesium board to test the changes. On the tx25 board TEXT_BASE is set to the final relocation address to prevent one more copying of u-boot code when relocating. More info see: doc/README.arm-relocation da850 board: Tested-by: Ben Gardiner <bengardiner@nanometrics.ca> Portions of this work were supported by funding from the CE Linux Forum. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Ben Gardiner <bengardiner@nanometrics.ca>
346 lines
7.5 KiB
C
346 lines
7.5 KiB
C
/*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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* Prafulla Wadaskar <prafulla@marvell.com>
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*
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* (C) Copyright 2009
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2010
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <common.h>
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#include <i2c.h>
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#include <nand.h>
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#include <netdev.h>
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#include <miiphy.h>
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#include <asm/io.h>
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#include <asm/arch/kirkwood.h>
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#include <asm/arch/mpp.h>
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#include "../common/common.h"
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DECLARE_GLOBAL_DATA_PTR;
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static int io_dev;
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extern I2C_MUX_DEVICE *i2c_mux_ident_muxstring (uchar *buf);
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/* Multi-Purpose Pins Functionality configuration */
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u32 kwmpp_config[] = {
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MPP0_NF_IO2,
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MPP1_NF_IO3,
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MPP2_NF_IO4,
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MPP3_NF_IO5,
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MPP4_NF_IO6,
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MPP5_NF_IO7,
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MPP6_SYSRST_OUTn,
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MPP7_PEX_RST_OUTn,
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#if defined(CONFIG_SOFT_I2C)
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MPP8_GPIO, /* SDA */
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MPP9_GPIO, /* SCL */
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#endif
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#if defined(CONFIG_HARD_I2C)
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MPP8_TW_SDA,
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MPP9_TW_SCK,
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#endif
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MPP10_UART0_TXD,
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MPP11_UART0_RXD,
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MPP12_GPO, /* Reserved */
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MPP13_UART1_TXD,
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MPP14_UART1_RXD,
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MPP15_GPIO, /* Not used */
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MPP16_GPIO, /* Not used */
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MPP17_GPIO, /* Reserved */
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MPP18_NF_IO0,
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MPP19_NF_IO1,
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MPP20_GPIO,
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MPP21_GPIO,
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MPP22_GPIO,
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MPP23_GPIO,
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MPP24_GPIO,
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MPP25_GPIO,
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MPP26_GPIO,
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MPP27_GPIO,
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MPP28_GPIO,
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MPP29_GPIO,
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MPP30_GPIO,
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MPP31_GPIO,
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MPP32_GPIO,
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MPP33_GPIO,
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MPP34_GPIO, /* CDL1 (input) */
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MPP35_GPIO, /* CDL2 (input) */
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MPP36_GPIO, /* MAIN_IRQ (input) */
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MPP37_GPIO, /* BOARD_LED */
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MPP38_GPIO, /* Piggy3 LED[1] */
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MPP39_GPIO, /* Piggy3 LED[2] */
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MPP40_GPIO, /* Piggy3 LED[3] */
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MPP41_GPIO, /* Piggy3 LED[4] */
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MPP42_GPIO, /* Piggy3 LED[5] */
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MPP43_GPIO, /* Piggy3 LED[6] */
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MPP44_GPIO, /* Piggy3 LED[7] */
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MPP45_GPIO, /* Piggy3 LED[8] */
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MPP46_GPIO, /* Reserved */
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MPP47_GPIO, /* Reserved */
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MPP48_GPIO, /* Reserved */
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MPP49_GPIO, /* SW_INTOUTn */
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0
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};
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int ethernet_present(void)
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{
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uchar buf;
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int ret = 0;
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if (i2c_read(0x10, 2, 1, &buf, 1) != 0) {
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printf ("%s: Error reading Boco\n", __FUNCTION__);
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return -1;
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}
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if ((buf & 0x40) == 0x40) {
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ret = 1;
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}
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return ret;
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}
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int misc_init_r(void)
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{
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I2C_MUX_DEVICE *i2cdev;
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char *str;
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int mach_type;
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/* add I2C Bus for I/O Expander */
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i2cdev = i2c_mux_ident_muxstring((uchar *)"pca9554a:70:a");
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io_dev = i2cdev->busid;
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puts("Piggy:");
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if (ethernet_present() == 0)
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puts (" not");
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puts(" present\n");
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str = getenv("mach_type");
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if (str != NULL) {
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mach_type = simple_strtoul(str, NULL, 10);
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printf("Overwriting MACH_TYPE with %d!!!\n", mach_type);
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gd->bd->bi_arch_number = mach_type;
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}
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return 0;
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}
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int board_init(void)
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{
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u32 tmp;
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kirkwood_mpp_conf(kwmpp_config);
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/*
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* The FLASH_GPIO_PIN switches between using a
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* NAND or a SPI FLASH. Set this pin on start
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* to NAND mode.
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*/
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tmp = readl(KW_GPIO0_BASE);
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writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
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tmp = readl(KW_GPIO0_BASE + 4);
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writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE + 4);
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printf("KM: setting NAND mode\n");
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/*
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* arch number of board
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*/
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gd->bd->bi_arch_number = MACH_TYPE_SUEN3;
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/* address of boot parameters */
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gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
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#if defined(CONFIG_SOFT_I2C)
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/* init the GPIO for I2C Bitbang driver */
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kw_gpio_set_valid(SUEN3_SDA_PIN, 1);
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kw_gpio_set_valid(SUEN3_SCL_PIN, 1);
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kw_gpio_direction_output(SUEN3_SDA_PIN, 0);
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kw_gpio_direction_output(SUEN3_SCL_PIN, 0);
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#endif
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#if defined(CONFIG_SYS_EEPROM_WREN)
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kw_gpio_set_valid(SUEN3_ENV_WP, 38);
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kw_gpio_direction_output(SUEN3_ENV_WP, 1);
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#endif
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return 0;
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}
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#if defined(CONFIG_CMD_SF)
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int do_spi_toggle(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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u32 tmp;
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if (argc < 2)
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return cmd_usage(cmdtp);
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if ((strcmp(argv[1], "off") == 0)) {
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printf("SPI FLASH disabled, NAND enabled\n");
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/* Multi-Purpose Pins Functionality configuration */
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kwmpp_config[0] = MPP0_NF_IO2;
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kwmpp_config[1] = MPP1_NF_IO3;
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kwmpp_config[2] = MPP2_NF_IO4;
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kwmpp_config[3] = MPP3_NF_IO5;
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kirkwood_mpp_conf(kwmpp_config);
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tmp = readl(KW_GPIO0_BASE);
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writel(tmp | FLASH_GPIO_PIN , KW_GPIO0_BASE);
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} else if ((strcmp(argv[1], "on") == 0)) {
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printf("SPI FLASH enabled, NAND disabled\n");
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/* Multi-Purpose Pins Functionality configuration */
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kwmpp_config[0] = MPP0_SPI_SCn;
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kwmpp_config[1] = MPP1_SPI_MOSI;
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kwmpp_config[2] = MPP2_SPI_SCK;
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kwmpp_config[3] = MPP3_SPI_MISO;
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kirkwood_mpp_conf(kwmpp_config);
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tmp = readl(KW_GPIO0_BASE);
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writel(tmp & (~FLASH_GPIO_PIN) , KW_GPIO0_BASE);
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} else {
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return cmd_usage(cmdtp);
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}
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return 0;
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}
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U_BOOT_CMD(
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spitoggle, 2, 0, do_spi_toggle,
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"En-/disable SPI FLASH access",
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"<on|off> - Enable (on) or disable (off) SPI FLASH access\n"
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);
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#endif
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#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
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int dram_init(void)
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{
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int i;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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gd->bd->bi_dram[i].start = kw_sdram_bar(i);
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gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
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kw_sdram_bs(i));
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}
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return 0;
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}
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#else
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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/* Fix this */
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gd->ram_size = get_ram_size((volatile void *)kw_sdram_bar(0),
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kw_sdram_bs(0));
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return 0;
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}
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void dram_init_banksize(void)
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{
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int i;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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gd->bd->bi_dram[i].start = kw_sdram_bar(i);
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gd->bd->bi_dram[i].size = kw_sdram_bs(i);
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gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i),
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kw_sdram_bs(i));
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}
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}
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#endif
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/* Configure and enable MV88E1118 PHY */
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void reset_phy(void)
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{
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char *name = "egiga0";
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if (miiphy_set_current_dev(name))
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return;
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/* reset the phy */
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miiphy_reset(name, CONFIG_PHY_BASE_ADR);
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}
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#if defined(CONFIG_HUSH_INIT_VAR)
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int hush_init_var (void)
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{
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ivm_read_eeprom ();
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return 0;
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}
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#endif
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#if defined(CONFIG_BOOTCOUNT_LIMIT)
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void bootcount_store (ulong a)
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{
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volatile ulong *save_addr;
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volatile ulong size = 0;
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int i;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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size += gd->bd->bi_dram[i].size;
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}
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save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
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writel(a, save_addr);
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writel(BOOTCOUNT_MAGIC, &save_addr[1]);
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}
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ulong bootcount_load (void)
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{
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volatile ulong *save_addr;
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volatile ulong size = 0;
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int i;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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size += gd->bd->bi_dram[i].size;
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}
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save_addr = (ulong*)(size - BOOTCOUNT_ADDR);
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if (readl(&save_addr[1]) != BOOTCOUNT_MAGIC)
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return 0;
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else
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return readl(save_addr);
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}
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#endif
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#if defined(CONFIG_SOFT_I2C)
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void set_sda (int state)
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{
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I2C_ACTIVE;
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I2C_SDA(state);
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}
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void set_scl (int state)
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{
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I2C_SCL(state);
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}
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int get_sda (void)
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{
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I2C_TRISTATE;
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return I2C_READ;
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}
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int get_scl (void)
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{
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return (kw_gpio_get_value(SUEN3_SCL_PIN) ? 1 : 0);
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}
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#endif
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#if defined(CONFIG_SYS_EEPROM_WREN)
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int eeprom_write_enable (unsigned dev_addr, int state)
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{
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kw_gpio_set_value(SUEN3_ENV_WP, !state);
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return !kw_gpio_get_value(SUEN3_ENV_WP);
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}
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#endif
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