u-boot-brain/include/asm-ppc
Timur Tabi 9ff32d8ccf mpc86xx: set the DDR BATs after calculating true DDR size
After determining how much DDR is actually in the system, set DBAT0 and
IBAT0 accordingly.  This ensures that the CPU won't attempt to access
(via speculation) addresses outside of actual memory.

On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB
and kept that way.  If the system has less than 2GB of memory (typical for
an MPC8610 HPCD), the CPU may attempt to access this memory during
speculation.  The zlib code is notorious for generating such memory reads,
and indeed on the MPC8610, uncompressing the Linux kernel causes a machine
check (without this patch).

Currently we are limited to power of two sized DDR since we only use a
single bat.  If a non-power of two size is used that is less than
CONFIG_MAX_MEM_MAPPED u-boot will crash.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2010-03-30 10:50:22 -05:00
..
4xx_pci.h ppc4xx: Consolidate pci_master_init() function 2009-11-19 11:35:34 +01:00
4xx_pcie.h
5xx_immap.h
8xx_immap.h
atomic.h
bitops.h Correct ffs/fls regression for PowerPC etc 2009-09-17 22:45:31 +02:00
byteorder.h
cache.h
config.h lmb: only force on arches that use it 2010-01-21 22:26:00 +01:00
cpm_85xx.h
cpm_8260.h
e300.h
errno.h
fsl_ddr_dimm_params.h
fsl_ddr_sdram.h fsl-ddr: add override for the Rtt_Wr 2010-01-05 13:49:27 -06:00
fsl_dma.h
fsl_i2c.h
fsl_law.h fsl_law: add SRIO2 target id and law_size_bits() macro 2010-01-05 13:49:09 -06:00
fsl_lbc.h ppc/p4080: Add p4080 platform immap definitions 2009-09-24 12:05:27 -05:00
fsl_pci.h ppc/8xxx: Remove is_fsl_pci_agent 2010-01-05 13:49:07 -06:00
fsl_serdes.h
global_data.h PPC: Record U-Boot's relocated address in RAM and show in bdinfo. 2010-03-11 23:49:16 +01:00
gpio.h
immap_83xx.h NET: Base support for etsec2.0 2010-01-05 13:49:04 -06:00
immap_85xx.h ppc/p4080: Add Corenet Platform Cache (CPC) registers 2010-01-05 13:52:00 -06:00
immap_86xx.h 86xx: Add support for 'cpu disable' command 2010-01-26 23:17:50 -06:00
immap_512x.h mpc512x: fix System Clock Control constants for USB1 & USB2 2009-10-18 23:04:05 +02:00
immap_8220.h
immap_8260.h
immap_qe.h
interrupt.h
io.h
iopin_8xx.h
iopin_85xx.h
iopin_8260.h
m8260_pci.h
mc146818rtc.h
mmu.h mpc86xx: set the DDR BATs after calculating true DDR size 2010-03-30 10:50:22 -05:00
mp.h
mpc8xxx_spi.h
mpc512x.h mpc512x: fix fixed_sdram() init code. 2009-10-08 00:23:12 +02:00
mpc8349_pci.h
pci_io.h
pnp.h
posix_types.h
ppc4xx_config.h
ppc4xx-ebc.h ppc4xx: Corrected EBC register bit definitions 2010-03-02 14:12:52 +01:00
ppc4xx-isram.h
ppc4xx-sdram.h ppc4xx: Merge PPC4xx DDR and DDR2 ECC handling 2009-10-02 13:53:37 +02:00
ppc4xx-uic.h ppc4xx: Convert PPC4xx UIC defines from lower case to upper case 2009-09-28 10:45:42 +02:00
processor.h 85xx: Fix enabling of L1 cache parity on secondary cores 2010-03-30 10:48:30 -05:00
ptrace.h
residual.h
sigcontext.h
signal.h
status_led.h
string.h
types.h
u-boot.h
unaligned.h
xilinx_irq.h