mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-23 19:39:44 +09:00
9171fc8172
All of the duplicated code for Blackfin processors and boot modes have been unified. After all, the core is the same for all processors, just the peripheral set differs (which gets handled in the drivers). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
428 lines
13 KiB
C
428 lines
13 KiB
C
/*
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* U-boot - Configuration file for BF537 STAMP board
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*/
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#ifndef __CONFIG_BF537_H__
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#define __CONFIG_BF537_H__
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#include <asm/blackfin-config-pre.h>
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#define CFG_LONGHELP 1
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_BAUDRATE 57600
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/* Set default serial console for bf537 */
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#define CONFIG_UART_CONSOLE 0
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#define CONFIG_BOOTDELAY 5
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/* define CONFIG_BF537_STAMP_LEDCMD to enable LED command*/
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/*#define CONFIG_BF537_STAMP_LEDCMD 1*/
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#define CONFIG_PANIC_HANG 1
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#define CONFIG_BFIN_CPU bf537-0.2
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#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
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#define CONFIG_BFIN_MAC
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/* This sets the default state of the cache on U-Boot's boot */
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#define CONFIG_ICACHE_ON
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#define CONFIG_DCACHE_ON
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/* Define if want to do post memory test */
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#undef CONFIG_POST_TEST
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#define CONFIG_RTC_BFIN 1
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#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
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/* CONFIG_CLKIN_HZ is any value in Hz */
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#define CONFIG_CLKIN_HZ 25000000
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/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
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/* 1=CLKIN/2 */
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#define CONFIG_CLKIN_HALF 0
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/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
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/* 1=bypass PLL*/
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#define CONFIG_PLL_BYPASS 0
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/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
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/* Values can range from 1-64 */
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#define CONFIG_VCO_MULT 20
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/* CONFIG_CCLK_DIV controls what the core clock divider is */
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/* Values can be 1, 2, 4, or 8 ONLY */
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#define CONFIG_CCLK_DIV 1
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/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
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/* Values can range from 1-15 */
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#define CONFIG_SCLK_DIV 5
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/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
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/* Values can range from 2-65535 */
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/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
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#define CONFIG_SPI_BAUD 2
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#define CONFIG_SPI_BAUD_INITBLOCK 4
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#if ( CONFIG_CLKIN_HALF == 0 )
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#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
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#else
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#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
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#endif
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#if (CONFIG_PLL_BYPASS == 0)
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#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
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#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
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#else
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#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
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#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
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#endif
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#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
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#define CONFIG_MEM_ADD_WDTH 10 /* 8, 9, 10, 11 */
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#define CONFIG_MEM_MT48LC32M8A2_75 1
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#define CONFIG_LOADS_ECHO 1
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/*
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* rarpb, bootp or dhcp commands will perform only a
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* configuration lookup from the BOOTP/DHCP server
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* but not try to load any image using TFTP
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*/
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#define CFG_AUTOLOAD "no"
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/*
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* Network Settings
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*/
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/* network support */
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#ifdef CONFIG_BFIN_MAC
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#define CONFIG_IPADDR 192.168.0.15
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_GATEWAYIP 192.168.0.1
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#define CONFIG_SERVERIP 192.168.0.2
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#define CONFIG_HOSTNAME BF537
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#endif
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#define CONFIG_ROOTPATH /romfs
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/* Uncomment next line to use fixed MAC address */
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/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
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/* This is the routine that copies the MAC in Flash to the 'ethaddr' setting */
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#define CFG_LONGHELP 1
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#define CONFIG_BOOTDELAY 5
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#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
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#define CONFIG_BOOTCOMMAND "run ramboot"
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#if defined(CONFIG_POST_TEST)
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/* POST support */
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#define CONFIG_POST ( CFG_POST_MEMORY | \
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CFG_POST_UART | \
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CFG_POST_FLASH | \
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CFG_POST_ETHER | \
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CFG_POST_LED | \
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CFG_POST_BUTTON)
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#else
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#undef CONFIG_POST
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#endif
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#ifdef CONFIG_POST
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#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
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#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
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#endif
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/* CF-CARD IDE-HDD Support */
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/* #define CONFIG_BFIN_TRUE_IDE */ /* Add CF flash card support */
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/* #define CONFIG_BFIN_CF_IDE */ /* Add CF flash card support */
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/* #define CONFIG_BFIN_HDD_IDE */ /* Add IDE Disk Drive (HDD) support */
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#if defined(CONFIG_BFIN_CF_IDE) || defined(CONFIG_BFIN_HDD_IDE) || defined(CONFIG_BFIN_TRUE_IDE)
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# define CONFIG_BFIN_IDE 1
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#endif
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/*#define CONFIG_BF537_NAND */ /* Add nand flash support */
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#define CONFIG_NETCONSOLE 1
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#define CONFIG_NET_MULTI 1
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_DATE
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#ifndef CONFIG_BFIN_MAC
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#undef CONFIG_CMD_NET
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#else
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#define CONFIG_CMD_PING
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#endif
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#if defined(CONFIG_BFIN_CF_IDE) \
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|| defined(CONFIG_BFIN_HDD_IDE) \
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|| defined(CONFIG_BFIN_TRUE_IDE)
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#define CONFIG_CMD_IDE
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#endif
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#define CONFIG_CMD_DHCP
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#if defined(CONFIG_POST)
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#define CONFIG_CMD_DIAG
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#endif
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#ifdef CONFIG_BF537_NAND
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#define CONFIG_CMD_NAND
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#endif
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#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
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#define CONFIG_LOADADDR 0x1000000
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$(serverip):$(rootpath) console=ttyBF0,57600\0"\
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"addip=setenv bootargs $(bootargs) " \
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"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
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":$(hostname):eth0:off\0" \
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"ramboot=tftpboot $(loadaddr) linux;" \
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"run ramargs;run addip;bootelf\0" \
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"nfsboot=tftpboot $(loadaddr) linux;" \
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"run nfsargs;run addip;bootelf\0" \
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"flashboot=bootm 0x20100000\0" \
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"update=tftpboot $(loadaddr) u-boot.bin;" \
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"protect off 0x20000000 0x2007FFFF;" \
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"erase 0x20000000 0x2007FFFF;cp.b 0x1000000 0x20000000 $(filesize)\0" \
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""
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#define CFG_PROMPT "bfin> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024*1024)
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_MEMTEST_START 0x0 /* memtest works on */
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#define CFG_MEMTEST_END ( (CONFIG_MEM_SIZE - 1) * 1024*1024) /* 1 ... 63 MB in DRAM */
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#define CFG_LOAD_ADDR CONFIG_LOADADDR /* default load address */
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#define CFG_HZ 1000 /* decrementer freq: 10 ms ticks */
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0x20000000
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#define CFG_FLASH_CFI /* The flash is CFI compatible */
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#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CFG_FLASH_PROTECTION
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#define CFG_MAX_FLASH_BANKS 1
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#define CFG_MAX_FLASH_SECT 71 /* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
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#define CFG_GBL_DATA_SIZE 0x4000
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#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
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#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
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#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
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#define CFG_ENV_IS_IN_EEPROM 1
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#define CFG_ENV_OFFSET 0x4000
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#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x16e) /* 0x12A is the length of LDR file header */
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#else
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR 0x20004000
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#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
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#endif
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#define CFG_ENV_SIZE 0x2000
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#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
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#define ENV_IS_EMBEDDED
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/* JFFS Partition offset set */
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#define CFG_JFFS2_FIRST_BANK 0
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#define CFG_JFFS2_NUM_BANKS 1
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/* 512k reserved for u-boot */
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#define CFG_JFFS2_FIRST_SECTOR 15
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#define CONFIG_SPI
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/*
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* Stack sizes
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*/
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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#define POLL_MODE 1
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#define FLASH_TOT_SECT 71
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#define FLASH_SIZE 0x400000
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#define CFG_FLASH_SIZE 0x400000
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/*
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* Board NAND Infomation
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*/
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#define CFG_NAND_ADDR 0x20212000
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#define CFG_NAND_BASE CFG_NAND_ADDR
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#define CFG_MAX_NAND_DEVICE 1
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#define SECTORSIZE 512
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#define ADDR_COLUMN 1
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#define ADDR_PAGE 2
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#define ADDR_COLUMN_PAGE 3
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#define NAND_ChipID_UNKNOWN 0x00
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#define NAND_MAX_FLOORS 1
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#define NAND_MAX_CHIPS 1
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#define BFIN_NAND_READY PF3
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#define NAND_WAIT_READY(nand) \
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do { \
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int timeout = 0; \
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while(!(*pPORTFIO & PF3)) \
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if (timeout++ > 100000) \
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break; \
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} while (0)
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#define BFIN_NAND_CLE (1<<2) /* A2 -> Command Enable */
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#define BFIN_NAND_ALE (1<<1) /* A1 -> Address Enable */
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#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_CLE) = (__u8)(d); } while(0)
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#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr | BFIN_NAND_ALE) = (__u8)(d); } while(0)
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#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
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#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
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/*
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* Initialize PSD4256 registers for using I2C
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*/
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#define CONFIG_MISC_INIT_R
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#define CFG_BOOTM_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
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/*
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* I2C settings
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* By default PF1 is used as SDA and PF0 as SCL on the Stamp board
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*/
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/* #define CONFIG_SOFT_I2C 1*/ /* I2C bit-banged */
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#define CONFIG_HARD_I2C 1 /* I2C TWI */
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#if defined CONFIG_HARD_I2C
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#define CONFIG_TWICLK_KHZ 50
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#endif
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#define CONFIG_EBIU_SDRRC_VAL 0x306
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#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
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#define CONFIG_EBIU_SDBCTL_VAL 0x25
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#define CONFIG_EBIU_AMGCTL_VAL 0xFF
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#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
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#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
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#if defined CONFIG_SOFT_I2C
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define PF_SCL PF0
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#define PF_SDA PF1
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#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
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#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
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#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
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#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
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#define I2C_SDA(bit) if(bit) { \
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*pFIO_FLAG_S = PF_SDA; \
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asm("ssync;"); \
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} \
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else { \
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*pFIO_FLAG_C = PF_SDA; \
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asm("ssync;"); \
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}
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#define I2C_SCL(bit) if(bit) { \
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*pFIO_FLAG_S = PF_SCL; \
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asm("ssync;"); \
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} \
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else { \
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*pFIO_FLAG_C = PF_SCL; \
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asm("ssync;"); \
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}
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#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
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#endif
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#define CFG_I2C_SPEED 50000
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#define CFG_I2C_SLAVE 0xFE
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/* 0xFF, 0x7BB07BB0, 0x22547BB0 */
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/* #define AMGCTLVAL (AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
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#define AMBCTL0VAL (B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B1TT_4 | ~B1RDYPOL | \
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~B1RDYEN | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3 | B0TT_4 | ~B0RDYPOL | ~B0RDYEN)
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#define AMBCTL1VAL (B3WAT_2 | B3RAT_2 | B3HT_1 | B3ST_1 | B3TT_4 | B3RDYPOL | ~B3RDYEN | \
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B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3 | B2TT_4 | ~B2RDYPOL | ~B2RDYEN)
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*/
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#define AMGCTLVAL 0xFF
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#define AMBCTL0VAL 0x7BB07BB0
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#define AMBCTL1VAL 0xFFC27BB0
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#if defined(CONFIG_BFIN_IDE)
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#define CONFIG_DOS_PARTITION 1
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/*
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* IDE/ATA stuff
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*/
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#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
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#undef CONFIG_IDE_LED /* no led for ide supported */
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#undef CONFIG_IDE_RESET /* no reset for ide supported */
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#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
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#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
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#undef AMBCTL1VAL
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#define AMBCTL1VAL 0xFFC3FFC3
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#define CONFIG_CF_ATASEL_DIS 0x20311800
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#define CONFIG_CF_ATASEL_ENA 0x20311802
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#if defined(CONFIG_BFIN_TRUE_IDE)
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/*
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* Note that these settings aren't for the most part used in include/ata.h
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* when all of the ATA registers are setup
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*/
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#define CFG_ATA_BASE_ADDR 0x2031C000
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#define CFG_ATA_IDE0_OFFSET 0x0000
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#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
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#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
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#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
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#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */
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#endif /* CONFIG_BFIN_TRUE_IDE */
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#if defined(CONFIG_BFIN_CF_IDE) /* USE CompactFlash Storage Card in the common memory space */
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#define CFG_ATA_BASE_ADDR 0x20211800
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#define CFG_ATA_IDE0_OFFSET 0x0000
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#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
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#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
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#define CFG_ATA_ALT_OFFSET 0x000E /* Offset for alternate registers */
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#define CFG_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */
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#endif /* CONFIG_BFIN_CF_IDE */
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#if defined(CONFIG_BFIN_HDD_IDE) /* USE TRUE IDE */
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#define CFG_ATA_BASE_ADDR 0x20314000
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#define CFG_ATA_IDE0_OFFSET 0x0000
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#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
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#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
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#define CFG_ATA_ALT_OFFSET 0x001C /* Offset for alternate registers */
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#define CFG_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
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#undef CONFIG_SCLK_DIV
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#define CONFIG_SCLK_DIV 8
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#endif /* CONFIG_BFIN_HDD_IDE */
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#endif /*CONFIG_BFIN_IDE */
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#include <asm/blackfin-config-post.h>
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#endif
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