mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-24 03:49:43 +09:00
9171fc8172
All of the duplicated code for Blackfin processors and boot modes have been unified. After all, the core is the same for all processors, just the peripheral set differs (which gets handled in the drivers). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
374 lines
9.9 KiB
C
374 lines
9.9 KiB
C
/*
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* U-boot - Configuration file for BF533 STAMP board
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*/
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#ifndef __CONFIG_STAMP_H__
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#define __CONFIG_STAMP_H__
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#include <asm/blackfin-config-pre.h>
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#define CONFIG_RTC_BFIN 1
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#define CONFIG_PANIC_HANG 1
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#define CONFIG_BFIN_CPU bf533-0.3
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#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
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/* This sets the default state of the cache on U-Boot's boot */
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#define CONFIG_ICACHE_ON
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#define CONFIG_DCACHE_ON
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/*
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* Board settings
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*/
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#define CONFIG_DRIVER_SMC91111 1
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#define CONFIG_SMC91111_BASE 0x20300300
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/* FLASH/ETHERNET uses the same address range */
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#define SHARED_RESOURCES 1
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/* Is I2C bit-banged? */
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#define CONFIG_SOFT_I2C 1
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/*
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* Software (bit-bang) I2C driver configuration
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*/
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#define PF_SCL PF3
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#define PF_SDA PF2
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/*
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* Video splash screen support
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*/
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#define CONFIG_VIDEO 0
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/*
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* Clock settings
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*/
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/* CONFIG_CLKIN_HZ is any value in Hz */
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#define CONFIG_CLKIN_HZ 11059200
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/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
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/* 1=CLKIN/2 */
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#define CONFIG_CLKIN_HALF 0
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/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
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/* 1=bypass PLL */
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#define CONFIG_PLL_BYPASS 0
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/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
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/* Values can range from 1-64 */
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#define CONFIG_VCO_MULT 36
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/* CONFIG_CCLK_DIV controls what the core clock divider is */
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/* Values can be 1, 2, 4, or 8 ONLY */
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#define CONFIG_CCLK_DIV 1
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/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
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/* Values can range from 1-15 */
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#define CONFIG_SCLK_DIV 5
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/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
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/* Values can range from 2-65535 */
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/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
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#define CONFIG_SPI_BAUD 2
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#define CONFIG_SPI_BAUD_INITBLOCK 4
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/*
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* Network settings
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*/
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#if (CONFIG_DRIVER_SMC91111)
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#if 0
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#define CONFIG_MII
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#endif
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/* network support */
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#define CONFIG_IPADDR 192.168.0.15
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#define CONFIG_NETMASK 255.255.255.0
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#define CONFIG_GATEWAYIP 192.168.0.1
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#define CONFIG_SERVERIP 192.168.0.2
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#define CONFIG_HOSTNAME STAMP
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#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs
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/* To remove hardcoding and enable MAC storage in EEPROM */
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/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
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#endif /* CONFIG_DRIVER_SMC91111 */
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/*
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* Flash settings
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*/
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#define CFG_FLASH_CFI /* The flash is CFI compatible */
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#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
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#define CFG_FLASH_CFI_AMD_RESET
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#define CFG_FLASH_BASE 0x20000000
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
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#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
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#define CFG_ENV_IS_IN_EEPROM 1
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#define CFG_ENV_OFFSET 0x4000
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#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x12A) /* 0x12A is the length of LDR file header */
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#else
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#define CFG_ENV_IS_IN_FLASH 1
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#define CFG_ENV_ADDR 0x20004000
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#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
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#endif
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#define CFG_ENV_SIZE 0x2000
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#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
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#define ENV_IS_EMBEDDED
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#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */
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#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
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/* JFFS Partition offset set */
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#define CFG_JFFS2_FIRST_BANK 0
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#define CFG_JFFS2_NUM_BANKS 1
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/* 512k reserved for u-boot */
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#define CFG_JFFS2_FIRST_SECTOR 11
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/*
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* following timeouts shall be used once the
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* Flash real protection is enabled
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*/
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#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
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#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
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/*
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* SDRAM settings & memory map
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*/
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#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */
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#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */
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#define CONFIG_MEM_MT48LC64M4A2FB_7E 1
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#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 *1024)
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#define CFG_MEMTEST_END (CFG_MAX_RAM_SIZE - 0x80000 - 1)
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#define CONFIG_LOADADDR 0x01000000
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#define CFG_LOAD_ADDR CONFIG_LOADADDR
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#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
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#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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#define CFG_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */
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#define CONFIG_STACKSIZE (128*1024) /* regular stack */
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#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - 0x40000)
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#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
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#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
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#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
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/* Check to make sure everything fits in SDRAM */
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#if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE)
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#error Memory Map does not fit into configuration
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#endif
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#if ( CONFIG_CLKIN_HALF == 0 )
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#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
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#else
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#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
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#endif
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#if (CONFIG_PLL_BYPASS == 0)
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#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
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#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
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#else
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#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
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#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
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#endif
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/*
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* Command settings
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*/
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#define CFG_LONGHELP 1
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#define CONFIG_CMDLINE_EDITING 1
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#define CFG_AUTOLOAD "no" /*rarpb, bootp or dhcp commands will perform only a */
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/* configuration lookup from the BOOTP/DHCP server, */
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/* but not try to load any image using TFTP */
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#define CONFIG_BOOTDELAY 5
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#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
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#define CONFIG_BOOTCOMMAND "run ramboot"
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#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
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"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
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"$(rootpath) console=ttyBF0,57600\0" \
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"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
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"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
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"ramboot=tftpboot $(loadaddr) linux; " \
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"run ramargs;run addip;bootelf\0" \
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"nfsboot=tftpboot $(loadaddr) linux; " \
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"run nfsargs;run addip;bootelf\0" \
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"flashboot=bootm 0x20100000\0" \
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"update=tftpboot $(loadaddr) u-boot.bin; " \
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"protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \
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"cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
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""
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#ifdef CONFIG_SOFT_I2C
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#if (!CONFIG_SOFT_I2C)
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#undef CONFIG_SOFT_I2C
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#endif
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#endif
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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/*
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* Command line configuration.
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*/
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#include <config_cmd_default.h>
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#define CONFIG_CMD_ELF
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#define CONFIG_CMD_CACHE
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_DATE
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#if (CONFIG_DRIVER_SMC91111)
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#define CONFIG_CMD_PING
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#endif
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#if (CONFIG_SOFT_I2C)
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#define CONFIG_CMD_I2C
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#endif
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#define CONFIG_CMD_DHCP
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/*
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* Console settings
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*/
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#define CONFIG_BAUDRATE 57600
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#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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#define CFG_PROMPT "bfin> " /* Monitor Command Prompt */
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#if defined(CONFIG_CMD_KGDB)
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#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
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#else
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#endif
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CONFIG_LOADS_ECHO 1
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/*
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* I2C settings
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* By default PF2 is used as SDA and PF3 as SCL on the Stamp board
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*/
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#if (CONFIG_SOFT_I2C)
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#define I2C_INIT (*pFIO_DIR |= PF_SCL); asm("ssync;")
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#define I2C_ACTIVE (*pFIO_DIR |= PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
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#define I2C_TRISTATE (*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
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#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
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#define I2C_SDA(bit) if(bit) { \
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*pFIO_FLAG_S = PF_SDA; \
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asm("ssync;"); \
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} \
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else { \
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*pFIO_FLAG_C = PF_SDA; \
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asm("ssync;"); \
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}
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#define I2C_SCL(bit) if(bit) { \
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*pFIO_FLAG_S = PF_SCL; \
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asm("ssync;"); \
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} \
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else { \
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*pFIO_FLAG_C = PF_SCL; \
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asm("ssync;"); \
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}
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#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
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#define CFG_I2C_SPEED 50000
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#define CFG_I2C_SLAVE 0xFE
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#endif /* CONFIG_SOFT_I2C */
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/*
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* Compact Flash settings
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*/
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/* Enabled below option for CF support */
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/* #define CONFIG_STAMP_CF 1 */
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#if defined(CONFIG_STAMP_CF) && defined(CONFIG_CMD_IDE)
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#define CONFIG_MISC_INIT_R 1
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#define CONFIG_DOS_PARTITION 1
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/*
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* IDE/ATA stuff
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*/
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#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
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#undef CONFIG_IDE_LED /* no led for ide supported */
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#undef CONFIG_IDE_RESET /* no reset for ide supported */
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#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
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#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
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#define CFG_ATA_BASE_ADDR 0x20200000
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#define CFG_ATA_IDE0_OFFSET 0x0000
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#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
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#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
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#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */
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#define CFG_ATA_STRIDE 2
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_HZ 1000 /* 1ms time tick */
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#define CFG_BOOTM_LEN 0x4000000/* Large Image Length, set to 64 Meg */
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#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
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#define CONFIG_SPI
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#ifdef CONFIG_VIDEO
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#if (CONFIG_VIDEO)
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#define CONFIG_SPLASH_SCREEN 1
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#define CONFIG_SILENT_CONSOLE 1
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#else
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#undef CONFIG_VIDEO
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#endif
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#endif
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/*
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* FLASH organization and environment definitions
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*/
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#define CONFIG_EBIU_SDRRC_VAL 0x268
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#define CONFIG_EBIU_SDGCTL_VAL 0x911109
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#define CONFIG_EBIU_SDBCTL_VAL 0x37
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#define CONFIG_EBIU_AMGCTL_VAL 0xFF
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#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
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#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
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#define CF_CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
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#include <asm/blackfin-config-post.h>
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#endif
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