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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
159 lines
3.7 KiB
C
159 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* From coreboot file of same name
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2014 Google, Inc
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/lapic.h>
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#include <asm/msr.h>
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#include <asm/msr-index.h>
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#include <asm/post.h>
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unsigned long lapic_read(unsigned long reg)
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{
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return readl(LAPIC_DEFAULT_BASE + reg);
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}
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#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
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sizeof(*(ptr))))
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struct __xchg_dummy { unsigned long a[100]; };
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#define __xg(x) ((struct __xchg_dummy *)(x))
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/*
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* Note: no "lock" prefix even on SMP. xchg always implies lock anyway.
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*
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* Note 2: xchg has side effect, so that attribute volatile is necessary,
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* but generally the primitive is invalid, *ptr is output argument.
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*/
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static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
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int size)
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{
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switch (size) {
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case 1:
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__asm__ __volatile__("xchgb %b0,%1"
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: "=q" (x)
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: "m" (*__xg(ptr)), "0" (x)
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: "memory");
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break;
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case 2:
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__asm__ __volatile__("xchgw %w0,%1"
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: "=r" (x)
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: "m" (*__xg(ptr)), "0" (x)
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: "memory");
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break;
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case 4:
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__asm__ __volatile__("xchgl %0,%1"
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: "=r" (x)
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: "m" (*__xg(ptr)), "0" (x)
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: "memory");
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break;
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}
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return x;
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}
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void lapic_write(unsigned long reg, unsigned long v)
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{
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(void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE + reg), v);
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}
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void enable_lapic(void)
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{
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if (!IS_ENABLED(CONFIG_INTEL_QUARK)) {
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msr_t msr;
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msr = msr_read(MSR_IA32_APICBASE);
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msr.hi &= 0xffffff00;
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msr.lo |= MSR_IA32_APICBASE_ENABLE;
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msr.lo &= ~MSR_IA32_APICBASE_BASE;
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msr.lo |= LAPIC_DEFAULT_BASE;
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msr_write(MSR_IA32_APICBASE, msr);
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}
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}
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void disable_lapic(void)
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{
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if (!IS_ENABLED(CONFIG_INTEL_QUARK)) {
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msr_t msr;
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msr = msr_read(MSR_IA32_APICBASE);
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msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
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msr_write(MSR_IA32_APICBASE, msr);
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}
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}
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unsigned long lapicid(void)
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{
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return lapic_read(LAPIC_ID) >> 24;
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}
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static void lapic_wait_icr_idle(void)
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{
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do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY);
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}
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int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
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{
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int timeout;
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unsigned long status;
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int result;
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lapic_wait_icr_idle();
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lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
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lapic_write(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
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timeout = 0;
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do {
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status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
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} while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
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result = -1;
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if (status == LAPIC_ICR_RR_VALID) {
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*pvalue = lapic_read(LAPIC_RRR);
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result = 0;
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}
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return result;
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}
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void lapic_setup(void)
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{
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/* Only Pentium Pro and later have those MSR stuff */
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debug("Setting up local apic: ");
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/* Enable the local apic */
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enable_lapic();
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/* Set Task Priority to 'accept all' */
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lapic_write(LAPIC_TASKPRI,
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lapic_read(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
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/* Put the local apic in virtual wire mode */
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lapic_write(LAPIC_SPIV, (lapic_read(LAPIC_SPIV) &
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~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
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lapic_write(LAPIC_LVT0, (lapic_read(LAPIC_LVT0) &
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~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
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LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
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LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
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LAPIC_DELIVERY_MODE_MASK)) |
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(LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
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LAPIC_DELIVERY_MODE_EXTINT));
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lapic_write(LAPIC_LVT1, (lapic_read(LAPIC_LVT1) &
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~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
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LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
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LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
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LAPIC_DELIVERY_MODE_MASK)) |
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(LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
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LAPIC_DELIVERY_MODE_NMI));
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debug("apic_id: 0x%02lx, ", lapicid());
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debug("done.\n");
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post_code(POST_LAPIC);
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}
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