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![Jernej Skrabec](/assets/img/avatar_default.png)
Add some basic line delay values to be used with DDR3 DRAM chips on some H6 TV boxes. Taken from a register dump after boot0 initialised the DRAM. Put them as the default delay values for DDR3 DRAM until we know better. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
657 lines
20 KiB
C
657 lines
20 KiB
C
/*
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* sun50i H6 platform dram controller init
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*
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* (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/dram.h>
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#include <asm/arch/cpu.h>
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#include <linux/bitops.h>
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#include <linux/kconfig.h>
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/*
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* The DRAM controller structure on H6 is similar to the ones on A23/A80:
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* they all contains 3 parts, COM, CTL and PHY. (As a note on A33/A83T/H3/A64
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* /H5/R40 CTL and PHY is composed).
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*
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* COM is allwinner-specific. On H6, the address mapping function is moved
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* from COM to CTL (with the standard ADDRMAP registers on DesignWare memory
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* controller).
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*
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* CTL (controller) and PHY is from DesignWare.
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*
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* The CTL part is a bit similar to the one on A23/A80 (because they all
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* originate from DesignWare), but gets more registers added.
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*
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* The PHY part is quite new, not seen in any previous Allwinner SoCs, and
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* not seen on other SoCs in U-Boot. The only SoC that is also known to have
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* similar PHY is ZynqMP.
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*/
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static void mctl_sys_init(struct dram_para *para);
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static void mctl_com_init(struct dram_para *para);
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static void mctl_channel_init(struct dram_para *para);
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static void mctl_core_init(struct dram_para *para)
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{
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mctl_sys_init(para);
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mctl_com_init(para);
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switch (para->type) {
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case SUNXI_DRAM_TYPE_LPDDR3:
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case SUNXI_DRAM_TYPE_DDR3:
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mctl_set_timing_params(para);
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break;
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default:
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panic("Unsupported DRAM type!");
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};
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mctl_channel_init(para);
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}
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/* PHY initialisation */
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static void mctl_phy_pir_init(u32 val)
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{
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struct sunxi_mctl_phy_reg * const mctl_phy =
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(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
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writel(val, &mctl_phy->pir);
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writel(val | BIT(0), &mctl_phy->pir); /* Start initialisation. */
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mctl_await_completion(&mctl_phy->pgsr[0], BIT(0), BIT(0));
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}
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enum {
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MBUS_PORT_CPU = 0,
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MBUS_PORT_GPU = 1,
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MBUS_PORT_MAHB = 2,
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MBUS_PORT_DMA = 3,
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MBUS_PORT_VE = 4,
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MBUS_PORT_CE = 5,
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MBUS_PORT_TSC0 = 6,
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MBUS_PORT_NDFC0 = 8,
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MBUS_PORT_CSI0 = 11,
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MBUS_PORT_DI0 = 14,
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MBUS_PORT_DI1 = 15,
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MBUS_PORT_DE300 = 16,
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MBUS_PORT_IOMMU = 25,
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MBUS_PORT_VE2 = 26,
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MBUS_PORT_USB3 = 37,
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MBUS_PORT_PCIE = 38,
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MBUS_PORT_VP9 = 39,
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MBUS_PORT_HDCP2 = 40,
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};
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enum {
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MBUS_QOS_LOWEST = 0,
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MBUS_QOS_LOW,
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MBUS_QOS_HIGH,
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MBUS_QOS_HIGHEST
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};
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inline void mbus_configure_port(u8 port,
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bool bwlimit,
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bool priority,
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u8 qos,
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u8 waittime,
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u8 acs,
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u16 bwl0,
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u16 bwl1,
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u16 bwl2)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0)
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| (priority ? (1 << 1) : 0)
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| ((qos & 0x3) << 2)
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| ((waittime & 0xf) << 4)
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| ((acs & 0xff) << 8)
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| (bwl0 << 16) );
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const u32 cfg1 = ((u32)bwl2 << 16) | (bwl1 & 0xffff);
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debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
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writel(cfg0, &mctl_com->master[port].cfg0);
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writel(cfg1, &mctl_com->master[port].cfg1);
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}
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#define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2) \
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mbus_configure_port(MBUS_PORT_ ## port, bwlimit, false, \
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MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)
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static void mctl_set_master_priority(void)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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/* enable bandwidth limit windows and set windows size 1us */
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writel(399, &mctl_com->tmr);
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writel(BIT(16), &mctl_com->bwcr);
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MBUS_CONF( CPU, true, HIGHEST, 0, 256, 128, 100);
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MBUS_CONF( GPU, true, HIGH, 0, 1536, 1400, 256);
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MBUS_CONF( MAHB, true, HIGHEST, 0, 512, 256, 96);
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MBUS_CONF( DMA, true, HIGH, 0, 256, 100, 80);
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MBUS_CONF( VE, true, HIGH, 2, 8192, 5500, 5000);
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MBUS_CONF( CE, true, HIGH, 2, 100, 64, 32);
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MBUS_CONF( TSC0, true, HIGH, 2, 100, 64, 32);
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MBUS_CONF(NDFC0, true, HIGH, 0, 256, 128, 64);
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MBUS_CONF( CSI0, true, HIGH, 0, 256, 128, 100);
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MBUS_CONF( DI0, true, HIGH, 0, 1024, 256, 64);
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MBUS_CONF(DE300, true, HIGHEST, 6, 8192, 2800, 2400);
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MBUS_CONF(IOMMU, true, HIGHEST, 0, 100, 64, 32);
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MBUS_CONF( VE2, true, HIGH, 2, 8192, 5500, 5000);
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MBUS_CONF( USB3, true, HIGH, 0, 256, 128, 64);
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MBUS_CONF( PCIE, true, HIGH, 2, 100, 64, 32);
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MBUS_CONF( VP9, true, HIGH, 2, 8192, 5500, 5000);
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MBUS_CONF(HDCP2, true, HIGH, 2, 100, 64, 32);
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}
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static void mctl_sys_init(struct dram_para *para)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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/* Put all DRAM-related blocks to reset state */
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clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE | MBUS_RESET);
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clrbits_le32(&ccm->dram_gate_reset, BIT(0));
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udelay(5);
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writel(0, &ccm->dram_gate_reset);
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clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
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clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
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udelay(5);
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/* Set PLL5 rate to doubled DRAM clock rate */
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writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN |
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CCM_PLL5_CTRL_N(para->clk * 2 / 24 - 1), &ccm->pll5_cfg);
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mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK);
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/* Configure DRAM mod clock */
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writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg);
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setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE);
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writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset);
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udelay(5);
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setbits_le32(&ccm->dram_gate_reset, BIT(0));
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/* Disable all channels */
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writel(0, &mctl_com->maer0);
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writel(0, &mctl_com->maer1);
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writel(0, &mctl_com->maer2);
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/* Configure MBUS and enable DRAM mod reset */
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setbits_le32(&ccm->mbus_cfg, MBUS_RESET);
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setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE);
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setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
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udelay(5);
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/* Unknown hack from the BSP, which enables access of mctl_ctl regs */
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writel(0x8000, &mctl_ctl->unk_0x00c);
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}
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static void mctl_set_addrmap(struct dram_para *para)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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u8 cols = para->cols;
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u8 rows = para->rows;
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u8 ranks = para->ranks;
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/* Ranks */
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if (ranks == 2)
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mctl_ctl->addrmap[0] = rows + cols - 3;
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else
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mctl_ctl->addrmap[0] = 0x1F;
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/* Banks, hardcoded to 8 banks now */
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mctl_ctl->addrmap[1] = (cols - 2) | (cols - 2) << 8 | (cols - 2) << 16;
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/* Columns */
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mctl_ctl->addrmap[2] = 0;
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switch (cols) {
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case 8:
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mctl_ctl->addrmap[3] = 0x1F1F0000;
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mctl_ctl->addrmap[4] = 0x1F1F;
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break;
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case 9:
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mctl_ctl->addrmap[3] = 0x1F000000;
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mctl_ctl->addrmap[4] = 0x1F1F;
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break;
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case 10:
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mctl_ctl->addrmap[3] = 0;
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mctl_ctl->addrmap[4] = 0x1F1F;
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break;
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case 11:
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mctl_ctl->addrmap[3] = 0;
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mctl_ctl->addrmap[4] = 0x1F00;
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break;
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case 12:
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mctl_ctl->addrmap[3] = 0;
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mctl_ctl->addrmap[4] = 0;
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break;
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default:
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panic("Unsupported DRAM configuration: column number invalid\n");
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}
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/* Rows */
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mctl_ctl->addrmap[5] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
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switch (rows) {
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case 13:
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mctl_ctl->addrmap[6] = (cols - 3) | 0x0F0F0F00;
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mctl_ctl->addrmap[7] = 0x0F0F;
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break;
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case 14:
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mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | 0x0F0F0000;
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mctl_ctl->addrmap[7] = 0x0F0F;
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break;
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case 15:
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mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | 0x0F000000;
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mctl_ctl->addrmap[7] = 0x0F0F;
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break;
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case 16:
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mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
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mctl_ctl->addrmap[7] = 0x0F0F;
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break;
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case 17:
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mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
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mctl_ctl->addrmap[7] = (cols - 3) | 0x0F00;
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break;
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case 18:
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mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
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mctl_ctl->addrmap[7] = (cols - 3) | ((cols - 3) << 8);
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break;
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default:
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panic("Unsupported DRAM configuration: row number invalid\n");
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}
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/* Bank groups, DDR4 only */
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mctl_ctl->addrmap[8] = 0x3F3F;
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}
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static void mctl_com_init(struct dram_para *para)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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struct sunxi_mctl_phy_reg * const mctl_phy =
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(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
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u32 reg_val, tmp;
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mctl_set_addrmap(para);
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setbits_le32(&mctl_com->cr, BIT(31));
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/* The bonding ID seems to be always 7. */
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if (readl(SUNXI_SIDC_BASE + 0x100) == 7) /* bonding ID */
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clrbits_le32(&mctl_com->cr, BIT(27));
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else if (readl(SUNXI_SIDC_BASE + 0x100) == 3)
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setbits_le32(&mctl_com->cr, BIT(27));
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if (para->clk > 408)
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reg_val = 0xf00;
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else if (para->clk > 246)
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reg_val = 0x1f00;
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else
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reg_val = 0x3f00;
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clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val);
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/* TODO: half DQ, DDR4 */
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reg_val = MSTR_BUSWIDTH_FULL | MSTR_BURST_LENGTH(8) |
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MSTR_ACTIVE_RANKS(para->ranks);
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if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
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reg_val |= MSTR_DEVICETYPE_LPDDR3;
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if (para->type == SUNXI_DRAM_TYPE_DDR3)
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reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE;
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writel(reg_val | BIT(31), &mctl_ctl->mstr);
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if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
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reg_val = DCR_LPDDR3 | DCR_DDR8BANK;
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if (para->type == SUNXI_DRAM_TYPE_DDR3)
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reg_val = DCR_DDR3 | DCR_DDR8BANK | DCR_DDR2T;
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writel(reg_val | 0x400, &mctl_phy->dcr);
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if (para->ranks == 2)
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writel(0x0303, &mctl_ctl->odtmap);
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else
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writel(0x0201, &mctl_ctl->odtmap);
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/* TODO: DDR4 */
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if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
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tmp = para->clk * 7 / 2000;
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reg_val = 0x0400;
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reg_val |= (tmp + 7) << 24;
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reg_val |= (((para->clk < 400) ? 3 : 4) - tmp) << 16;
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} else if (para->type == SUNXI_DRAM_TYPE_DDR3) {
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reg_val = 0x06000400; /* TODO?: Use CL - CWL value in [7:0] */
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} else {
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panic("Only (LP)DDR3 supported (type = %d)\n", para->type);
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}
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writel(reg_val, &mctl_ctl->odtcfg);
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/* TODO: half DQ */
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}
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static void mctl_bit_delay_set(struct dram_para *para)
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{
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struct sunxi_mctl_phy_reg * const mctl_phy =
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(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
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int i, j;
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u32 val;
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for (i = 0; i < 4; i++) {
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val = readl(&mctl_phy->dx[i].bdlr0);
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for (j = 0; j < 4; j++)
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val += para->dx_write_delays[i][j] << (j * 8);
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writel(val, &mctl_phy->dx[i].bdlr0);
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val = readl(&mctl_phy->dx[i].bdlr1);
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for (j = 0; j < 4; j++)
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val += para->dx_write_delays[i][j + 4] << (j * 8);
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writel(val, &mctl_phy->dx[i].bdlr1);
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val = readl(&mctl_phy->dx[i].bdlr2);
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for (j = 0; j < 4; j++)
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val += para->dx_write_delays[i][j + 8] << (j * 8);
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writel(val, &mctl_phy->dx[i].bdlr2);
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}
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clrbits_le32(&mctl_phy->pgcr[0], BIT(26));
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for (i = 0; i < 4; i++) {
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val = readl(&mctl_phy->dx[i].bdlr3);
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for (j = 0; j < 4; j++)
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val += para->dx_read_delays[i][j] << (j * 8);
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writel(val, &mctl_phy->dx[i].bdlr3);
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val = readl(&mctl_phy->dx[i].bdlr4);
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for (j = 0; j < 4; j++)
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val += para->dx_read_delays[i][j + 4] << (j * 8);
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writel(val, &mctl_phy->dx[i].bdlr4);
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val = readl(&mctl_phy->dx[i].bdlr5);
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for (j = 0; j < 4; j++)
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val += para->dx_read_delays[i][j + 8] << (j * 8);
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writel(val, &mctl_phy->dx[i].bdlr5);
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val = readl(&mctl_phy->dx[i].bdlr6);
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val += (para->dx_read_delays[i][12] << 8) |
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(para->dx_read_delays[i][13] << 16);
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writel(val, &mctl_phy->dx[i].bdlr6);
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}
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setbits_le32(&mctl_phy->pgcr[0], BIT(26));
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udelay(1);
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if (para->type != SUNXI_DRAM_TYPE_LPDDR3)
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return;
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for (i = 1; i < 14; i++) {
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val = readl(&mctl_phy->acbdlr[i]);
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val += 0x0a0a0a0a;
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writel(val, &mctl_phy->acbdlr[i]);
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}
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}
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static void mctl_channel_init(struct dram_para *para)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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struct sunxi_mctl_phy_reg * const mctl_phy =
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(struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
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int i;
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u32 val;
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setbits_le32(&mctl_ctl->dfiupd[0], BIT(31) | BIT(30));
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setbits_le32(&mctl_ctl->zqctl[0], BIT(31) | BIT(30));
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writel(0x2f05, &mctl_ctl->sched[0]);
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setbits_le32(&mctl_ctl->rfshctl3, BIT(0));
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setbits_le32(&mctl_ctl->dfimisc, BIT(0));
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setbits_le32(&mctl_ctl->unk_0x00c, BIT(8));
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clrsetbits_le32(&mctl_phy->pgcr[1], 0x180, 0xc0);
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/* TODO: non-LPDDR3 types */
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clrsetbits_le32(&mctl_phy->pgcr[2], GENMASK(17, 0), ns_to_t(7800));
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clrbits_le32(&mctl_phy->pgcr[6], BIT(0));
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clrsetbits_le32(&mctl_phy->dxccr, 0xee0, 0x220);
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/* TODO: VT compensation */
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clrsetbits_le32(&mctl_phy->dsgcr, BIT(0), 0x440060);
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clrbits_le32(&mctl_phy->vtcr[1], BIT(1));
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for (i = 0; i < 4; i++)
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clrsetbits_le32(&mctl_phy->dx[i].gcr[0], 0xe00, 0x800);
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for (i = 0; i < 4; i++)
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clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, 0x5555);
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for (i = 0; i < 4; i++)
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clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, 0x1010);
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udelay(100);
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if (para->ranks == 2)
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setbits_le32(&mctl_phy->dtcr[1], 0x30000);
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else
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clrsetbits_le32(&mctl_phy->dtcr[1], 0x30000, 0x10000);
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if (sunxi_dram_is_lpddr(para->type))
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clrbits_le32(&mctl_phy->dtcr[1], BIT(1));
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if (para->ranks == 2) {
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writel(0x00010001, &mctl_phy->rankidr);
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writel(0x20000, &mctl_phy->odtcr);
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} else {
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writel(0x0, &mctl_phy->rankidr);
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writel(0x10000, &mctl_phy->odtcr);
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}
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/* set bits [3:0] to 1? 0 not valid in ZynqMP d/s */
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if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
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clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000040);
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else
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clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000000);
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if (para->clk <= 792) {
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if (para->clk <= 672) {
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if (para->clk <= 600)
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val = 0x300;
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else
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val = 0x400;
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} else {
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val = 0x500;
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}
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} else {
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val = 0x600;
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}
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/* FIXME: NOT REVIEWED YET */
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clrsetbits_le32(&mctl_phy->zq[0].zqcr, 0x700, val);
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clrsetbits_le32(&mctl_phy->zq[0].zqpr[0], 0xff,
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CONFIG_DRAM_ZQ & 0xff);
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clrbits_le32(&mctl_phy->zq[0].zqor[0], 0xfffff);
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setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ >> 8) & 0xff);
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setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xf00) - 0x100);
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setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xff00) << 4);
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clrbits_le32(&mctl_phy->zq[1].zqpr[0], 0xfffff);
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setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ >> 16) & 0xff);
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setbits_le32(&mctl_phy->zq[1].zqpr[0], ((CONFIG_DRAM_ZQ >> 8) & 0xf00) - 0x100);
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setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ & 0xff0000) >> 4);
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if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
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for (i = 1; i < 14; i++)
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writel(0x06060606, &mctl_phy->acbdlr[i]);
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}
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val = PIR_ZCAL | PIR_DCAL | PIR_PHYRST | PIR_DRAMINIT | PIR_QSGATE |
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PIR_RDDSKW | PIR_WRDSKW | PIR_RDEYE | PIR_WREYE;
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if (para->type == SUNXI_DRAM_TYPE_DDR3)
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val |= PIR_DRAMRST | PIR_WL;
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mctl_phy_pir_init(val);
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/* TODO: DDR4 types ? */
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for (i = 0; i < 4; i++)
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writel(0x00000909, &mctl_phy->dx[i].gcr[5]);
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for (i = 0; i < 4; i++) {
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if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
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val = 0x0;
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else
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val = 0xaaaa;
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clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, val);
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if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
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val = 0x0;
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else
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val = 0x2020;
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clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, val);
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}
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mctl_bit_delay_set(para);
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udelay(1);
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setbits_le32(&mctl_phy->pgcr[6], BIT(0));
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clrbits_le32(&mctl_phy->pgcr[6], 0xfff8);
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for (i = 0; i < 4; i++)
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clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff);
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udelay(10);
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if (readl(&mctl_phy->pgsr[0]) & 0x400000)
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{
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/*
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* Detect single rank.
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* TODO: also detect half DQ.
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*/
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if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 &&
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(readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2 &&
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(readl(&mctl_phy->dx[2].rsr[0]) & 0x3) == 2 &&
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(readl(&mctl_phy->dx[3].rsr[0]) & 0x3) == 2) {
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para->ranks = 1;
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/* Restart DRAM initialization from scratch. */
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mctl_core_init(para);
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return;
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}
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else {
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panic("This DRAM setup is currently not supported.\n");
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}
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}
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if (readl(&mctl_phy->pgsr[0]) & 0xff00000) {
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/* Oops! There's something wrong! */
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debug("PLL = %x\n", readl(0x3001010));
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debug("DRAM PHY PGSR0 = %x\n", readl(&mctl_phy->pgsr[0]));
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for (i = 0; i < 4; i++)
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debug("DRAM PHY DX%dRSR0 = %x\n", i, readl(&mctl_phy->dx[i].rsr[0]));
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panic("Error while initializing DRAM PHY!\n");
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}
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if (sunxi_dram_is_lpddr(para->type))
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clrsetbits_le32(&mctl_phy->dsgcr, 0xc0, 0x40);
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clrbits_le32(&mctl_phy->pgcr[1], 0x40);
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clrbits_le32(&mctl_ctl->dfimisc, BIT(0));
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writel(1, &mctl_ctl->swctl);
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mctl_await_completion(&mctl_ctl->swstat, 1, 1);
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clrbits_le32(&mctl_ctl->rfshctl3, BIT(0));
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setbits_le32(&mctl_com->unk_0x014, BIT(31));
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writel(0xffffffff, &mctl_com->maer0);
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writel(0x7ff, &mctl_com->maer1);
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writel(0xffff, &mctl_com->maer2);
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}
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static void mctl_auto_detect_dram_size(struct dram_para *para)
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{
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/* TODO: non-LPDDR3, half DQ */
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/*
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* Detect rank number by the code in mctl_channel_init. Furtherly
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* when DQ detection is available it will also be executed there.
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*/
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mctl_core_init(para);
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/* detect row address bits */
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para->cols = 8;
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para->rows = 18;
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mctl_core_init(para);
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for (para->rows = 13; para->rows < 18; para->rows++) {
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/* 8 banks, 8 bit per byte and 32 bit width */
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if (mctl_mem_matches((1 << (para->rows + para->cols + 5))))
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break;
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}
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/* detect column address bits */
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para->cols = 11;
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mctl_core_init(para);
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for (para->cols = 8; para->cols < 11; para->cols++) {
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/* 8 bits per byte and 32 bit width */
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if (mctl_mem_matches(1 << (para->cols + 2)))
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break;
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}
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}
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unsigned long mctl_calc_size(struct dram_para *para)
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{
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/* TODO: non-LPDDR3, half DQ */
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/* 8 banks, 32-bit (4 byte) data width */
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return (1ULL << (para->cols + para->rows + 3)) * 4 * para->ranks;
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}
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#define SUN50I_H6_LPDDR3_DX_WRITE_DELAYS \
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{{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 0 }, \
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
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#define SUN50I_H6_LPDDR3_DX_READ_DELAYS \
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{{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
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{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
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{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
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{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }}
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#define SUN50I_H6_DDR3_DX_WRITE_DELAYS \
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{{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
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#define SUN50I_H6_DDR3_DX_READ_DELAYS \
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{{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
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{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
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unsigned long sunxi_dram_init(void)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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struct dram_para para = {
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.clk = CONFIG_DRAM_CLK,
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.ranks = 2,
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.cols = 11,
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.rows = 14,
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#ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
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.type = SUNXI_DRAM_TYPE_LPDDR3,
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.dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS,
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.dx_write_delays = SUN50I_H6_LPDDR3_DX_WRITE_DELAYS,
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#elif defined(CONFIG_SUNXI_DRAM_H6_DDR3_1333)
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.type = SUNXI_DRAM_TYPE_DDR3,
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.dx_read_delays = SUN50I_H6_DDR3_DX_READ_DELAYS,
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.dx_write_delays = SUN50I_H6_DDR3_DX_WRITE_DELAYS,
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#endif
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};
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unsigned long size;
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/* RES_CAL_CTRL_REG in BSP U-boot*/
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setbits_le32(0x7010310, BIT(8));
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clrbits_le32(0x7010318, 0x3f);
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mctl_auto_detect_dram_size(¶);
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mctl_core_init(¶);
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size = mctl_calc_size(¶);
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clrsetbits_le32(&mctl_com->cr, 0xf0, (size >> (10 + 10 + 4)) & 0xf0);
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mctl_set_master_priority();
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return size;
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};
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