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https://github.com/brain-hackers/u-boot-brain
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34a8258fea
Add support for initializing the SERDES blocks on CoreNet style QoriQ devices and the p4080 specific SERDES tables to know which actual componetns are enabled. Additionally, split out the Frame Manger (FMAN) into its specific ethernet ports instead of gross level of the full FMAN. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
57 lines
1.3 KiB
C
57 lines
1.3 KiB
C
/*
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* Copyright 2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __FSL_SERDES_H
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#define __FSL_SERDES_H
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#include <config.h>
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enum srds_prtcl {
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NONE = 0,
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PCIE1,
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PCIE2,
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PCIE3,
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PCIE4,
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SATA1,
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SATA2,
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SRIO1,
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SRIO2,
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SGMII_FM1_DTSEC1,
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SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3,
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SGMII_FM1_DTSEC4,
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SGMII_FM1_DTSEC5,
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SGMII_FM2_DTSEC1,
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SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3,
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SGMII_FM2_DTSEC4,
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SGMII_TSEC1,
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SGMII_TSEC2,
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SGMII_TSEC3,
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SGMII_TSEC4,
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XAUI_FM1,
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XAUI_FM2,
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AURORA,
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};
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int is_serdes_configured(enum srds_prtcl device);
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void fsl_serdes_init(void);
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#endif /* __FSL_SERDES_H */
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