mirror of
https://github.com/brain-hackers/u-boot-brain
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2e5167ccad
By now, the majority of architectures have working relocation support, so the few remaining architectures have become exceptions. To make this more obvious, we make working relocation now the default case, and flag the remaining cases with CONFIG_NEEDS_MANUAL_RELOC. Signed-off-by: Wolfgang Denk <wd@denx.de> Tested-by: Heiko Schocher <hs@denx.de> Tested-by: Reinhard Meyer <u-boot@emk-elektronik.de>
102 lines
3.0 KiB
C
102 lines
3.0 KiB
C
/*
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* Copyright 2009-2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef _ASM_CONFIG_H_
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#define _ASM_CONFIG_H_
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#define CONFIG_LMB
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#define CONFIG_SYS_BOOT_RAMDISK_HIGH
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#define CONFIG_SYS_BOOT_GET_CMDLINE
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#define CONFIG_SYS_BOOT_GET_KBD
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#ifndef CONFIG_MAX_MEM_MAPPED
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#if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
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#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
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#else
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#define CONFIG_MAX_MEM_MAPPED (256 << 20)
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#endif
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#endif
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/* Check if boards need to enable FSL DMA engine for SDRAM init */
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#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
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#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
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((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
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!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
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#define CONFIG_FSL_DMA
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#endif
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#endif
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#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \
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defined(CONFIG_P1021) || defined(CONFIG_P1022) || \
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defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
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#define CONFIG_MAX_CPUS 2
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#elif defined(CONFIG_PPC_P3041)
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#define CONFIG_MAX_CPUS 4
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#elif defined(CONFIG_PPC_P4080)
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#define CONFIG_MAX_CPUS 8
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#elif defined(CONFIG_PPC_P5020)
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#define CONFIG_MAX_CPUS 2
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#else
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#define CONFIG_MAX_CPUS 1
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#endif
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/*
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* Provide a default boot page translation virtual address that lines up with
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* Freescale's default e500 reset page.
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*/
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#if (defined(CONFIG_E500) && defined(CONFIG_MP))
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#ifndef CONFIG_BPTR_VIRT_ADDR
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#define CONFIG_BPTR_VIRT_ADDR 0xfffff000
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#endif
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#endif
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/* Enable TSEC2.0 for the platforms that have it if we are using TSEC */
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#if defined(CONFIG_TSEC_ENET) && \
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(defined(CONFIG_P1020) || defined(CONFIG_P1011))
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#define CONFIG_TSECV2
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#endif
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/*
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* SEC (crypto unit) major compatible version determination
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*/
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#if defined(CONFIG_FSL_CORENET)
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#elif defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83xx)
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#endif
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/* Number of TLB CAM entries we have on FSL Book-E chips */
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#if defined(CONFIG_E500MC)
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#define CONFIG_SYS_NUM_TLBCAMS 64
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#elif defined(CONFIG_E500)
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#define CONFIG_SYS_NUM_TLBCAMS 16
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#endif
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/* Since so many PPC SOCs have a semi-common LBC, define this here */
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#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
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defined(CONFIG_MPC83xx)
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#define CONFIG_FSL_LBC
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#endif
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/* All PPC boards must swap IDE bytes */
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#define CONFIG_IDE_SWAP_IO
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#endif /* _ASM_CONFIG_H_ */
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