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https://github.com/brain-hackers/u-boot-brain
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d9abba8254
This patch adds generic support for the Samsung s3c2440 processor. Global s3c24x0 changes to struct members converting from upper case to lower case. Signed-off-by: Craig Nauman <cnauman@diagraph.com> Cc: kevin.morfitt@fearnside-systems.co.uk Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
149 lines
5.1 KiB
C
149 lines
5.1 KiB
C
/*
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* Functions to access the TSC2000 controller on TRAB board (used for scanning
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* thermo sensors)
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*
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* Copyright (C) 2003 Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
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*
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* Copyright (C) 2002 DENX Software Engineering, Wolfgang Denk, wd@denx.de
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _TSC2000_H_
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#define _TSC2000_H_
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/* temperature channel multiplexer definitions */
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#define CON_MUX0 (gpio->pccon = (gpio->pccon & 0x0FFFFFCFF) | 0x00000100)
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#define CLR_MUX0 (gpio->pcdat &= 0x0FFEF)
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#define SET_MUX0 (gpio->pcdat |= 0x00010)
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#define CON_MUX1 (gpio->pccon = (gpio->pccon & 0x0FFFFF3FF) | 0x00000400)
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#define CLR_MUX1 (gpio->pcdat &= 0x0FFDF)
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#define SET_MUX1 (gpio->pcdat |= 0x00020)
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#define CON_MUX1_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFFFCFFF) | 0x00001000)
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#define CLR_MUX1_ENABLE (gpio->pcdat |= 0x00040)
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#define SET_MUX1_ENABLE (gpio->pcdat &= 0x0FFBF)
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#define CON_MUX2_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFFF3FFF) | 0x00004000)
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#define CLR_MUX2_ENABLE (gpio->pcdat |= 0x00080)
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#define SET_MUX2_ENABLE (gpio->pcdat &= 0x0FF7F)
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#define CON_MUX3_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFFCFFFF) | 0x00010000)
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#define CLR_MUX3_ENABLE (gpio->pcdat |= 0x00100)
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#define SET_MUX3_ENABLE (gpio->pcdat &= 0x0FEFF)
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#define CON_MUX4_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFF3FFFF) | 0x00040000)
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#define CLR_MUX4_ENABLE (gpio->pcdat |= 0x00200)
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#define SET_MUX4_ENABLE (gpio->pcdat &= 0x0FDFF)
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#define CON_SEL_TEMP_V_0 (gpio->pccon = (gpio->pccon & 0x0FFCFFFFF) | \
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0x00100000)
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#define CLR_SEL_TEMP_V_0 (gpio->pcdat &= 0x0FBFF)
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#define SET_SEL_TEMP_V_0 (gpio->pcdat |= 0x00400)
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#define CON_SEL_TEMP_V_1 (gpio->pccon = (gpio->pccon & 0x0FF3FFFFF) | \
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0x00400000)
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#define CLR_SEL_TEMP_V_1 (gpio->pcdat &= 0x0F7FF)
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#define SET_SEL_TEMP_V_1 (gpio->pcdat |= 0x00800)
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#define CON_SEL_TEMP_V_2 (gpio->pccon = (gpio->pccon & 0x0FCFFFFFF) | \
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0x01000000)
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#define CLR_SEL_TEMP_V_2 (gpio->pcdat &= 0x0EFFF)
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#define SET_SEL_TEMP_V_2 (gpio->pcdat |= 0x01000)
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#define CON_SEL_TEMP_V_3 (gpio->pccon = (gpio->pccon & 0x0F3FFFFFF) | \
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0x04000000)
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#define CLR_SEL_TEMP_V_3 (gpio->pcdat &= 0x0DFFF)
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#define SET_SEL_TEMP_V_3 (gpio->pcdat |= 0x02000)
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/* TSC2000 register definition */
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#define TSC2000_REG_X ((0 << 11) | (0 << 5))
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#define TSC2000_REG_Y ((0 << 11) | (1 << 5))
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#define TSC2000_REG_Z1 ((0 << 11) | (2 << 5))
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#define TSC2000_REG_Z2 ((0 << 11) | (3 << 5))
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#define TSC2000_REG_BAT1 ((0 << 11) | (5 << 5))
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#define TSC2000_REG_BAT2 ((0 << 11) | (6 << 5))
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#define TSC2000_REG_AUX1 ((0 << 11) | (7 << 5))
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#define TSC2000_REG_AUX2 ((0 << 11) | (8 << 5))
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#define TSC2000_REG_TEMP1 ((0 << 11) | (9 << 5))
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#define TSC2000_REG_TEMP2 ((0 << 11) | (0xA << 5))
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#define TSC2000_REG_DAC ((0 << 11) | (0xB << 5))
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#define TSC2000_REG_ZERO ((0 << 11) | (0x10 << 5))
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#define TSC2000_REG_ADC ((1 << 11) | (0 << 5))
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#define TSC2000_REG_DACCTL ((1 << 11) | (2 << 5))
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#define TSC2000_REG_REF ((1 << 11) | (3 << 5))
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#define TSC2000_REG_RESET ((1 << 11) | (4 << 5))
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#define TSC2000_REG_CONFIG ((1 << 11) | (5 << 5))
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/* bit definition of TSC2000 ADC register */
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#define TC_PSM (1 << 15)
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#define TC_STS (1 << 14)
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#define TC_AD3 (1 << 13)
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#define TC_AD2 (1 << 12)
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#define TC_AD1 (1 << 11)
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#define TC_AD0 (1 << 10)
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#define TC_RS1 (1 << 9)
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#define TC_RS0 (1 << 8)
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#define TC_AV1 (1 << 7)
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#define TC_AV0 (1 << 6)
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#define TC_CL1 (1 << 5)
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#define TC_CL0 (1 << 4)
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#define TC_PV2 (1 << 3)
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#define TC_PV1 (1 << 2)
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#define TC_PV0 (1 << 1)
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/* default value for TSC2000 ADC register for use with touch functions */
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#define DEFAULT_ADC (TC_PV1 | TC_AV0 | TC_AV1 | TC_RS0)
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#define TSC2000_DELAY_BASE 500
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#define TSC2000_NO_SENSOR -0x10000
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#define ERROR_BATTERY 220 /* must be adjusted, if R68 is changed on TRAB */
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void tsc2000_write(unsigned short, unsigned short);
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unsigned short tsc2000_read (unsigned short);
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u16 tsc2000_read_channel (unsigned int);
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void tsc2000_set_mux (unsigned int);
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void tsc2000_set_range (unsigned int);
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void tsc2000_reg_init (void);
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s32 tsc2000_contact_temp (void);
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void spi_wait_transmit_done (void);
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void tsc2000_spi_init(void);
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int tsc2000_interpolate(long value, long data[][2], long *result);
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void adc_wait_conversion_done(void);
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static inline void SET_CS_TOUCH(void)
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{
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struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
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gpio->pddat &= 0x5FF;
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}
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static inline void CLR_CS_TOUCH(void)
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{
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struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
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gpio->pddat |= 0x200;
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}
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#endif /* _TSC2000_H_ */
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