York Sun 379c5145ef powerpc/corenet2: fix mismatch DDR sync bit from RCW ... Corenet 2nd generation Chassis doesn't have ddr_sync bit in RCW. Only async mode is supported. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>		2012-10-22 14:31:20 -05:00
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cpu	powerpc/corenet2: fix mismatch DDR sync bit from RCW	2012-10-22 14:31:20 -05:00
include/asm	powerpc/corenet2: Add SerDes for corenet2	2012-10-22 14:31:19 -05:00
lib	split mpc8xx hooks from cmd_ide.c	2012-10-17 07:59:08 -07:00
config.mk	Handle most LDSCRIPT setting centrally	2011-04-30 00:59:47 +02:00