mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
aa36c84edf
For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC.
In non-secure boot scenario from NAND, this address will map to CPC
configured as SRAM. But in case of secure boot, this default address
always maps to IBR (Internal Boot ROM).
The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G
address space i.e. 0x0 - 0xDFFFFFFF.
For secure boot target from NAND, the text base for SPL is kept same as
non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will
be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000)
As a the virtual and physical address of CPC would be different. The
virtual address 0xFFFx_xxxx needs to be mapped to physical address
0xBFFx_xxxx.
Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000
and update DCFG SCRTACH1 register with location of Header required for
secure boot.
The changes are similar to
commit 467a40dfe3
powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041
While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC
is only 256K and thus SPL framework is used.
The changes are only applicable for SPL U-Boot running out of CPC SRAM
and not the next level U-Boot loaded on DDR.
Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com>
Signed-off-by: Sumit Garg <sumit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
161 lines
4.4 KiB
C
161 lines
4.4 KiB
C
/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_SECURE_BOOT_H
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#define __FSL_SECURE_BOOT_H
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#include <asm/config_mpc85xx.h>
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#ifdef CONFIG_SECURE_BOOT
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#ifndef CONFIG_FIT_SIGNATURE
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#define CONFIG_CHAIN_OF_TRUST
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#endif
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#if defined(CONFIG_FSL_CORENET)
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#define CONFIG_SYS_PBI_FLASH_BASE 0xc0000000
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#elif defined(CONFIG_BSC9132QDS)
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#define CONFIG_SYS_PBI_FLASH_BASE 0xc8000000
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#elif defined(CONFIG_C29XPCIE)
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#define CONFIG_SYS_PBI_FLASH_BASE 0xcc000000
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#else
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#define CONFIG_SYS_PBI_FLASH_BASE 0xce000000
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#endif
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#define CONFIG_SYS_PBI_FLASH_WINDOW 0xcff80000
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#if defined(CONFIG_B4860QDS) || \
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defined(CONFIG_T4240QDS) || \
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defined(CONFIG_T2080QDS) || \
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defined(CONFIG_T2080RDB) || \
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defined(CONFIG_T1040QDS) || \
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defined(CONFIG_T104xD4QDS) || \
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defined(CONFIG_T104xRDB) || \
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defined(CONFIG_T104xD4RDB) || \
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defined(CONFIG_PPC_T1023) || \
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defined(CONFIG_PPC_T1024)
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#ifndef CONFIG_SYS_RAMBOOT
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#define CONFIG_SYS_CPC_REINIT_F
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#endif
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#define CONFIG_KEY_REVOCATION
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#undef CONFIG_SYS_INIT_L3_ADDR
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#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
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#endif
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#if defined(CONFIG_RAMBOOT_PBL)
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#undef CONFIG_SYS_INIT_L3_ADDR
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#ifdef CONFIG_SYS_INIT_L3_VADDR
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#define CONFIG_SYS_INIT_L3_ADDR \
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(CONFIG_SYS_INIT_L3_VADDR & ~0xFFF00000) | \
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0xbff00000
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#else
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#define CONFIG_SYS_INIT_L3_ADDR 0xbff00000
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#endif
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#endif
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#if defined(CONFIG_C29XPCIE)
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#define CONFIG_KEY_REVOCATION
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#endif
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#if defined(CONFIG_PPC_P3041) || \
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defined(CONFIG_PPC_P4080) || \
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defined(CONFIG_PPC_P5020) || \
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defined(CONFIG_PPC_P5040) || \
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defined(CONFIG_PPC_P2041)
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#define CONFIG_FSL_TRUST_ARCH_v1
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#endif
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#if defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_RAMBOOT)
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/* The key used for verification of next level images
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* is picked up from an Extension Table which has
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* been verified by the ISBC (Internal Secure boot Code)
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* in boot ROM of the SoC.
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* The feature is only applicable in case of NOR boot and is
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* not applicable in case of RAMBOOT (NAND, SD, SPI).
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*/
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#define CONFIG_FSL_ISBC_KEY_EXT
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#endif
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#endif /* #ifdef CONFIG_SECURE_BOOT */
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#ifdef CONFIG_CHAIN_OF_TRUST
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SPL_DM 1
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#define CONFIG_SPL_CRYPTO_SUPPORT
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#define CONFIG_SPL_HASH_SUPPORT
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#define CONFIG_SPL_RSA
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#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
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/*
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* PPAACT and SPAACT table for PAMU must be placed on DDR after DDR init
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* due to space crunch on CPC and thus malloc will not work.
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*/
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#define CONFIG_SPL_PPAACT_ADDR 0x2e000000
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#define CONFIG_SPL_SPAACT_ADDR 0x2f000000
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#define CONFIG_SPL_JR0_LIODN_S 454
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#define CONFIG_SPL_JR0_LIODN_NS 458
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/*
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* Define the key hash for U-Boot here if public/private key pair used to
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* sign U-boot are different from the SRK hash put in the fuse
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* Example of defining KEY_HASH is
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* #define CONFIG_SPL_UBOOT_KEY_HASH \
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* "41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b"
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* else leave it defined as NULL
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*/
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#define CONFIG_SPL_UBOOT_KEY_HASH NULL
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#endif /* ifdef CONFIG_SPL_BUILD */
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#define CONFIG_CMD_ESBC_VALIDATE
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#define CONFIG_CMD_BLOB
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#define CONFIG_FSL_SEC_MON
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#define CONFIG_SHA_PROG_HW_ACCEL
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#define CONFIG_RSA_FREESCALE_EXP
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#ifndef CONFIG_FSL_CAAM
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#define CONFIG_FSL_CAAM
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#endif
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#ifndef CONFIG_SPL_BUILD
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/*
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* fsl_setenv_chain_of_trust() must be called from
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* board_late_init()
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*/
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#ifndef CONFIG_BOARD_LATE_INIT
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#define CONFIG_BOARD_LATE_INIT
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#endif
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/* If Boot Script is not on NOR and is required to be copied on RAM */
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#ifdef CONFIG_BOOTSCRIPT_COPY_RAM
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#define CONFIG_BS_HDR_ADDR_RAM 0x00010000
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#define CONFIG_BS_HDR_ADDR_FLASH 0x00800000
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#define CONFIG_BS_HDR_SIZE 0x00002000
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#define CONFIG_BS_ADDR_RAM 0x00012000
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#define CONFIG_BS_ADDR_FLASH 0x00802000
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#define CONFIG_BS_SIZE 0x00001000
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#define CONFIG_BOOTSCRIPT_HDR_ADDR CONFIG_BS_HDR_ADDR_RAM
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#else
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/* The bootscript header address is different for B4860 because the NOR
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* mapping is different on B4 due to reduced NOR size.
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*/
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#if defined(CONFIG_B4860QDS)
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xecc00000
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#elif defined(CONFIG_FSL_CORENET)
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xe8e00000
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#elif defined(CONFIG_BSC9132QDS)
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0x88020000
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#elif defined(CONFIG_C29XPCIE)
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xec020000
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#else
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#define CONFIG_BOOTSCRIPT_HDR_ADDR 0xee020000
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#endif
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#endif /* #ifdef CONFIG_BOOTSCRIPT_COPY_RAM */
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#include <config_fsl_chain_trust.h>
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#endif /* #ifndef CONFIG_SPL_BUILD */
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#endif /* #ifdef CONFIG_CHAIN_OF_TRUST */
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#endif
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