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https://github.com/brain-hackers/u-boot-brain
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712cf7ab0b
It is not necessary to keep multiple entries for the same setting in DDR speed tables. Merge them for smaller tables. Also restructure the tables for smaller size. Cleanup some typedefs. Enforce strict checking for speed table. If DIMM is running at higher than known speed, try to use the highest speed setting. If rank is unknown, it has to panic. Removed ODT overriding for P2020DS as it is not necessary. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
141 lines
3.4 KiB
C
141 lines
3.4 KiB
C
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <i2c.h>
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#include <hwconfig.h>
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#include <asm/mmu.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/fsl_ddr_dimm_params.h>
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#include <asm/fsl_law.h>
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struct board_specific_parameters {
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u32 n_ranks;
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u32 datarate_mhz_high;
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u32 clk_adjust;
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u32 wrlvl_start;
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u32 cpo;
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u32 write_data_delay;
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u32 force_2T;
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};
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/*
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* This table contains all valid speeds we want to override with board
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* specific parameters. datarate_mhz_high values need to be in ascending order
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* for each n_ranks group.
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*
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* ranges for parameters:
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* wr_data_delay = 0-6
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* clk adjust = 0-8
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* cpo 2-0x1E (30)
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*/
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static const struct board_specific_parameters dimm0[] = {
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/*
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* memory controller 0
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* num| hi| clk| wrlvl | cpo |wrdata|2T
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* ranks| mhz|adjst| start | delay|
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*/
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{2, 750, 3, 5, 0xff, 2, 0},
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{2, 1250, 4, 6, 0xff, 2, 0},
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{2, 1350, 5, 7, 0xff, 2, 0},
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{2, 1666, 5, 8, 0xff, 2, 0},
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{}
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};
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
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ulong ddr_freq;
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if (ctrl_num) {
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printf("Wrong parameter for controller number %d", ctrl_num);
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return;
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}
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if (!pdimm->n_ranks)
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return;
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pbsp = dimm0;
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/*
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* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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while (pbsp->datarate_mhz_high) {
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if (pbsp->n_ranks == pdimm->n_ranks) {
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if (ddr_freq <= pbsp->datarate_mhz_high) {
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popts->cpo_override = pbsp->cpo;
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popts->write_data_delay =
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pbsp->write_data_delay;
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popts->clk_adjust = pbsp->clk_adjust;
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popts->wrlvl_start = pbsp->wrlvl_start;
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popts->twoT_en = pbsp->force_2T;
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goto found;
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}
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pbsp_highest = pbsp;
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}
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pbsp++;
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}
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if (pbsp_highest) {
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printf("Error: board specific timing not found "
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"for data rate %lu MT/s!\n"
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"Trying to use the highest speed (%u) parameters\n",
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ddr_freq, pbsp_highest->datarate_mhz_high);
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popts->cpo_override = pbsp_highest->cpo;
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popts->write_data_delay = pbsp_highest->write_data_delay;
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popts->clk_adjust = pbsp_highest->clk_adjust;
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popts->wrlvl_start = pbsp_highest->wrlvl_start;
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popts->twoT_en = pbsp_highest->force_2T;
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} else {
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panic("DIMM is not supported by this board");
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}
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found:
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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/* Write leveling override */
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xf;
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/* Rtt and Rtt_WR override */
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popts->rtt_override = 0;
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/* Enable ZQ calibration */
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popts->zq_en = 1;
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/* DHC_EN =1, ODT = 60 Ohm */
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
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}
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phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size = 0;
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puts("Initializing....");
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if (fsl_use_spd()) {
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puts("using SPD\n");
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dram_size = fsl_ddr_sdram();
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} else {
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puts("no SPD and fixed parameters\n");
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return dram_size;
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}
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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debug(" DDR: ");
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return dram_size;
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}
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