mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
453 lines
12 KiB
C
453 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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* Author: Sandeep Kumar Singh <sandeep@freescale.com>
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*/
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/* This file is based on board/freescale/corenet_ds/eth_superhydra.c */
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/*
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* This file handles the board muxing between the Fman Ethernet MACs and
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* the RGMII/SGMII/XGMII PHYs on a Freescale B4860 "Centaur". The SGMII
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* PHYs are the two on-board 1Gb ports. There are no RGMII PHY on board.
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* The 10Gb XGMII PHY is provided via the XAUI riser card. There is only
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* one Fman device on B4860. The SERDES configuration is used to determine
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* where the SGMII and XAUI cards exist, and also which Fman MACs are routed
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* to which PHYs. So for a given Fman MAC, there is one and only PHY it
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* connects to. MACs cannot be routed to PHYs dynamically. This configuration
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* is done at boot time by reading SERDES protocol from RCW.
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/fsl_serdes.h>
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#include <fm_eth.h>
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#include <fsl_mdio.h>
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#include <malloc.h>
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#include <fdt_support.h>
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#include <fsl_dtsec.h>
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#include "../common/ngpixis.h"
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#include "../common/fman.h"
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#include "../common/qixis.h"
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#include "b4860qds_qixis.h"
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#define EMI_NONE 0xFFFFFFFF
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#ifdef CONFIG_FMAN_ENET
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/*
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* Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that
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* lane at index is mapped to slot number n. A value of '0' will mean
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* that the mapping must be determined dynamically, or that the lane maps to
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* something other than a board slot
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*/
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static u8 lane_to_slot[] = {
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0, 0, 0, 0,
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0, 0, 0, 0,
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1, 1, 1, 1,
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0, 0, 0, 0
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};
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/*
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* This function initializes the lane_to_slot[] array. It reads RCW to check
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* if Serdes2{E,F,G,H} is configured as slot 2 or as SFP and initializes
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* lane_to_slot[] accordingly
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*/
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static void initialize_lane_to_slot(void)
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{
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unsigned int serdes2_prtcl;
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
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serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
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debug("Initializing lane to slot: Serdes2 protocol: %x\n",
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serdes2_prtcl);
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switch (serdes2_prtcl) {
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case 0x17:
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case 0x18:
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/*
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* Configuration:
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* SERDES: 2
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* Lanes: A,B,C,D: SGMII
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* Lanes: E,F: Aur
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* Lanes: G,H: SRIO
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*/
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case 0x91:
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/*
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* Configuration:
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* SERDES: 2
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* Lanes: A,B: SGMII
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* Lanes: C,D: SRIO2
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* Lanes: E,F,G,H: XAUI2
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*/
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case 0x93:
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/*
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* Configuration:
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* SERDES: 2
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* Lanes: A,B,C,D: SGMII
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* Lanes: E,F,G,H: XAUI2
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*/
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case 0x98:
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/*
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* Configuration:
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* SERDES: 2
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* Lanes: A,B,C,D: XAUI2
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* Lanes: E,F,G,H: XAUI2
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*/
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case 0x9a:
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/*
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* Configuration:
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* SERDES: 2
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* Lanes: A,B: PCI
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* Lanes: C,D: SGMII
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* Lanes: E,F,G,H: XAUI2
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*/
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case 0x9e:
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/*
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* Configuration:
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* SERDES: 2
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* Lanes: A,B,C,D: PCI
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* Lanes: E,F,G,H: XAUI2
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*/
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case 0xb1:
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case 0xb2:
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case 0x8c:
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case 0x8d:
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/*
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* Configuration:
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* SERDES: 2
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* Lanes: A,B,C,D: PCI
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* Lanes: E,F: SGMII 3&4
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* Lanes: G,H: XFI
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*/
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case 0xc2:
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/*
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* Configuration:
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* SERDES: 2
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* Lanes: A,B: SGMII
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* Lanes: C,D: SRIO2
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* Lanes: E,F,G,H: XAUI2
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*/
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lane_to_slot[12] = 2;
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lane_to_slot[13] = lane_to_slot[12];
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lane_to_slot[14] = lane_to_slot[12];
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lane_to_slot[15] = lane_to_slot[12];
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break;
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default:
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printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
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serdes2_prtcl);
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break;
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}
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return;
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}
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#endif /* #ifdef CONFIG_FMAN_ENET */
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int board_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_FMAN_ENET
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struct memac_mdio_info memac_mdio_info;
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struct memac_mdio_info tg_memac_mdio_info;
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unsigned int i;
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unsigned int serdes1_prtcl, serdes2_prtcl;
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int qsgmii;
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struct mii_dev *bus;
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
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if (!serdes1_prtcl) {
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printf("SERDES1 is not enabled\n");
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return 0;
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}
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serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
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debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
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serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
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if (!serdes2_prtcl) {
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printf("SERDES2 is not enabled\n");
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return 0;
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}
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serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
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debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
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printf("Initializing Fman\n");
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initialize_lane_to_slot();
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memac_mdio_info.regs =
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(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
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memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
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/* Register the real 1G MDIO bus */
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fm_memac_mdio_init(bis, &memac_mdio_info);
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tg_memac_mdio_info.regs =
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(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
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tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
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/* Register the real 10G MDIO bus */
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fm_memac_mdio_init(bis, &tg_memac_mdio_info);
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/*
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* Program the two on board DTSEC PHY addresses assuming that they are
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* all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
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* 6 to on board SGMII phys
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*/
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fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
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fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
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switch (serdes1_prtcl) {
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case 0x29:
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case 0x2a:
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/* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
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debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n",
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CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
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CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
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fm_info_set_phy_address(FM1_DTSEC5,
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CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
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fm_info_set_phy_address(FM1_DTSEC6,
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CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
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break;
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#ifdef CONFIG_ARCH_B4420
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case 0x17:
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case 0x18:
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/* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
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debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n",
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CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
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CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
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/* Fixing Serdes clock by programming FPGA register */
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QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
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fm_info_set_phy_address(FM1_DTSEC3,
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CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
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fm_info_set_phy_address(FM1_DTSEC4,
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CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
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break;
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#endif
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default:
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printf("Fman: Unsupported SerDes1 Protocol 0x%02x\n",
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serdes1_prtcl);
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break;
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}
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switch (serdes2_prtcl) {
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case 0x17:
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case 0x18:
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debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
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CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC1,
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CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC2,
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CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC3,
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CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC4,
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CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR);
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break;
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case 0x48:
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case 0x49:
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debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
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CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC1,
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CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC2,
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CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC3,
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CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
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break;
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case 0xb1:
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case 0xb2:
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case 0x8c:
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case 0x8d:
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debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n",
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CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC3,
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CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
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fm_info_set_phy_address(FM1_DTSEC4,
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CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
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/*
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* XFI does not need a PHY to work, but to make U-Boot
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* happy, assign a fake PHY address for a XFI port.
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*/
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fm_info_set_phy_address(FM1_10GEC1, 0);
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fm_info_set_phy_address(FM1_10GEC2, 1);
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break;
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case 0x98:
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/* XAUI in Slot1 and Slot2 */
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debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n",
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CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
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fm_info_set_phy_address(FM1_10GEC1,
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CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
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debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
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CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
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fm_info_set_phy_address(FM1_10GEC2,
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CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
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break;
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case 0x9E:
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/* XAUI in Slot2 */
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debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
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CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
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fm_info_set_phy_address(FM1_10GEC2,
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CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
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break;
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default:
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printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
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serdes2_prtcl);
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break;
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}
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/*set PHY address for QSGMII Riser Card on slot2*/
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bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
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qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM, REGNUM);
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if (qsgmii) {
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switch (serdes2_prtcl) {
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case 0xb2:
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case 0x8d:
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fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR);
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fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
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break;
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default:
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break;
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}
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}
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for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
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int idx = i - FM1_DTSEC1;
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switch (fm_info_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_SGMII:
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fm_info_set_mdio(i,
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miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
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break;
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case PHY_INTERFACE_MODE_NONE:
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fm_info_set_phy_address(i, 0);
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break;
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default:
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printf("Fman1: DTSEC%u set to unknown interface %i\n",
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idx + 1, fm_info_get_enet_if(i));
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fm_info_set_phy_address(i, 0);
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break;
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}
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}
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for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
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int idx = i - FM1_10GEC1;
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switch (fm_info_get_enet_if(i)) {
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case PHY_INTERFACE_MODE_XGMII:
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fm_info_set_mdio(i,
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miiphy_get_dev_by_name
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(DEFAULT_FM_TGEC_MDIO_NAME));
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break;
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case PHY_INTERFACE_MODE_NONE:
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fm_info_set_phy_address(i, 0);
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break;
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default:
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printf("Fman1: TGEC%u set to unknown interface %i\n",
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idx + 1, fm_info_get_enet_if(i));
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fm_info_set_phy_address(i, 0);
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break;
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}
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}
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cpu_eth_init(bis);
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#endif
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return pci_eth_init(bis);
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}
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void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
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enum fm_port port, int offset)
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{
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int phy;
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char alias[32];
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struct fixed_link f_link;
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
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prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
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if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
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phy = fm_info_get_phy_address(port);
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sprintf(alias, "phy_sgmii_%x", phy);
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fdt_set_phy_handle(fdt, compat, addr, alias);
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fdt_status_okay_by_alias(fdt, alias);
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} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
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/* check if it's XFI interface for 10g */
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switch (prtcl2) {
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case 0x80:
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case 0x81:
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case 0x82:
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case 0x83:
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case 0x84:
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case 0x85:
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case 0x86:
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case 0x87:
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case 0x88:
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case 0x89:
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case 0x8a:
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case 0x8b:
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case 0x8c:
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case 0x8d:
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case 0x8e:
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case 0xb1:
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case 0xb2:
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f_link.phy_id = port;
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f_link.duplex = 1;
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f_link.link_speed = 10000;
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f_link.pause = 0;
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f_link.asym_pause = 0;
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fdt_delprop(fdt, offset, "phy-handle");
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fdt_setprop(fdt, offset, "fixed-link", &f_link,
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sizeof(f_link));
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break;
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case 0x98: /* XAUI interface */
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strcpy(alias, "phy_xaui_slot1");
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fdt_status_okay_by_alias(fdt, alias);
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strcpy(alias, "phy_xaui_slot2");
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fdt_status_okay_by_alias(fdt, alias);
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break;
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case 0x9e: /* XAUI interface */
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case 0x9a:
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case 0x93:
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case 0x91:
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strcpy(alias, "phy_xaui_slot1");
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fdt_status_okay_by_alias(fdt, alias);
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break;
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case 0x97: /* XAUI interface */
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case 0xc3:
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strcpy(alias, "phy_xaui_slot2");
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fdt_status_okay_by_alias(fdt, alias);
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break;
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default:
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break;
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}
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}
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}
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/*
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* Set status to disabled for unused ethernet node
|
|
*/
|
|
void fdt_fixup_board_enet(void *fdt)
|
|
{
|
|
int i;
|
|
char alias[32];
|
|
|
|
for (i = FM1_DTSEC1; i <= FM1_10GEC2; i++) {
|
|
switch (fm_info_get_enet_if(i)) {
|
|
case PHY_INTERFACE_MODE_NONE:
|
|
sprintf(alias, "ethernet%u", i);
|
|
fdt_status_disabled_by_alias(fdt, alias);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|