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https://github.com/brain-hackers/u-boot-brain
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a9a4b685de
These are mostly specific to a particular SoC. Add the definitions for Apollo Lake. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
124 lines
2.3 KiB
C
124 lines
2.3 KiB
C
/* SPDX-License-Identifier: Intel */
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/*
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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* Copyright 2019 Google LLC
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*/
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#ifndef __ASM_ARCH_FSP_M_UDP_H
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#define __ASM_ARCH_FSP_M_UDP_H
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#include <asm/fsp2/fsp_api.h>
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#define FSP_DRAM_CHANNELS 4
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struct __packed fspm_arch_upd {
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u8 revision;
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u8 reserved[3];
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void *nvs_buffer_ptr;
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void *stack_base;
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u32 stack_size;
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u32 boot_loader_tolum_size;
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u32 boot_mode;
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u8 reserved1[8];
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};
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struct __packed fsp_ram_channel {
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u8 rank_enable;
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u8 device_width;
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u8 dram_density;
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u8 option;
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u8 odt_config;
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u8 tristate_clk1;
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u8 mode2_n;
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u8 odt_levels;
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};
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struct __packed fsp_m_config {
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u32 serial_debug_port_address;
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u8 serial_debug_port_type;
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u8 serial_debug_port_device;
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u8 serial_debug_port_stride_size;
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u8 mrc_fast_boot;
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u8 igd;
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u8 igd_dvmt50_pre_alloc;
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u8 igd_aperture_size;
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u8 gtt_size;
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u8 primary_video_adaptor;
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u8 package;
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u8 profile;
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u8 memory_down;
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u8 ddr3_l_page_size;
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u8 ddr3_lasr;
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u8 scrambler_support;
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u8 interleaved_mode;
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u16 channel_hash_mask;
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u16 slice_hash_mask;
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u8 channels_slices_enable;
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u8 min_ref_rate2x_enable;
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u8 dual_rank_support_enable;
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u8 rmt_mode;
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u16 memory_size_limit;
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u16 low_memory_max_value;
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u16 high_memory_max_value;
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u8 disable_fast_boot;
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u8 dimm0_spd_address;
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u8 dimm1_spd_address;
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struct fsp_ram_channel chan[FSP_DRAM_CHANNELS];
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u8 rmt_check_run;
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u16 rmt_margin_check_scale_high_threshold;
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u8 ch_bit_swizzling[FSP_DRAM_CHANNELS][32];
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u32 msg_level_mask;
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u8 unused_upd_space0[4];
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u8 pre_mem_gpio_table_pin_num[4];
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u32 pre_mem_gpio_table_ptr;
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u8 pre_mem_gpio_table_entry_num;
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u8 enhance_port8xh_decoding;
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u8 spd_write_enable;
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u8 mrc_data_saving;
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u32 oem_loading_base;
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u8 oem_file_name[16];
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void *mrc_boot_data_ptr;
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u8 e_mmc_trace_len;
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u8 skip_cse_rbp;
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u8 npk_en;
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u8 fw_trace_en;
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u8 fw_trace_destination;
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u8 recover_dump;
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u8 msc0_wrap;
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u8 msc1_wrap;
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u32 msc0_size;
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u32 msc1_size;
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u8 pti_mode;
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u8 pti_training;
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u8 pti_speed;
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u8 punit_mlvl;
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u8 pmc_mlvl;
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u8 sw_trace_en;
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u8 periodic_retraining_disable;
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u8 enable_reset_system;
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u8 enable_s3_heci2;
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u8 unused_upd_space1[3];
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void *variable_nvs_buffer_ptr;
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u8 reserved_fspm_upd[12];
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};
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/** FSP-M UPD Configuration */
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struct __packed fspm_upd {
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struct fsp_upd_header header;
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struct fspm_arch_upd arch;
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struct fsp_m_config config;
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u8 unused_upd_space2[158];
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u16 upd_terminator;
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};
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#endif
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