Shengzhou Liu a994b3deb0 driver/ddr/fsl: Add workaround for A009663 ... Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0 before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE] to the desired value after DDR initialization has completed. When DDR controller is configured to operate in auto-precharge mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>		2016-01-25 08:24:15 -08:00
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altera	ddr: altera: Init the rule ID in debug code	2016-01-16 07:07:22 +01:00
fsl	driver/ddr/fsl: Add workaround for A009663	2016-01-25 08:24:15 -08:00
marvell	mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BIT	2016-01-14 14:08:59 +01:00