mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-18 07:58:52 +09:00
664 lines
16 KiB
C
664 lines
16 KiB
C
/*
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* (C) Copyright 2001
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* Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/* sdram_init.c - automatic memory sizing */
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#include <common.h>
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#include <74xx_7xx.h>
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#include <galileo/memory.h>
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#include <galileo/pci.h>
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#include <galileo/gt64260R.h>
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#include <net.h>
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#include "eth.h"
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#include "mpsc.h"
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#include "i2c.h"
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#include "64260.h"
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DECLARE_GLOBAL_DATA_PTR;
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/* #define DEBUG */
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#define MAP_PCI
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#ifdef DEBUG
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#define DP(x) x
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#else
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#define DP(x)
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#endif
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#define GB (1 << 30)
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/* structure to store the relevant information about an sdram bank */
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typedef struct sdram_info {
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uchar drb_size;
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uchar registered, ecc;
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uchar tpar;
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uchar tras_clocks;
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uchar burst_len;
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uchar banks, slot;
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int size; /* detected size, not from I2C but from dram_size() */
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} sdram_info_t;
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#ifdef DEBUG
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void dump_dimm_info (struct sdram_info *d)
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{
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static const char *ecc_legend[] = { "", " Parity", " ECC" };
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printf ("dimm%s %sDRAM: %dMibytes:\n",
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ecc_legend[d->ecc],
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d->registered ? "R" : "", (d->size >> 20));
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printf (" drb=%d tpar=%d tras=%d burstlen=%d banks=%d slot=%d\n",
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d->drb_size, d->tpar, d->tras_clocks, d->burst_len,
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d->banks, d->slot);
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}
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#endif
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static int
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memory_map_bank (unsigned int bankNo,
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unsigned int bankBase, unsigned int bankLength)
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{
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#ifdef DEBUG
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if (bankLength > 0) {
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printf ("mapping bank %d at %08x - %08x\n",
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bankNo, bankBase, bankBase + bankLength - 1);
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} else {
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printf ("unmapping bank %d\n", bankNo);
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}
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#endif
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memoryMapBank (bankNo, bankBase, bankLength);
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return 0;
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}
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#ifdef MAP_PCI
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static int
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memory_map_bank_pci (unsigned int bankNo,
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unsigned int bankBase, unsigned int bankLength)
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{
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PCI_HOST host;
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for (host = PCI_HOST0; host <= PCI_HOST1; host++) {
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const int features =
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PREFETCH_ENABLE |
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DELAYED_READ_ENABLE |
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AGGRESSIVE_PREFETCH |
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READ_LINE_AGGRESSIVE_PREFETCH |
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READ_MULTI_AGGRESSIVE_PREFETCH |
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MAX_BURST_4 | PCI_NO_SWAP;
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pciMapMemoryBank (host, bankNo, bankBase, bankLength);
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pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase,
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bankLength);
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pciSetRegionFeatures (host, bankNo, features, bankBase,
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bankLength);
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}
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return 0;
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}
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#endif
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/* ------------------------------------------------------------------------- */
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/* much of this code is based on (or is) the code in the pip405 port */
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/* thanks go to the authors of said port - Josh */
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/*
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* translate ns.ns/10 coding of SPD timing values
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* into 10 ps unit values
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*/
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static inline unsigned short NS10to10PS (unsigned char spd_byte)
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{
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unsigned short ns, ns10;
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/* isolate upper nibble */
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ns = (spd_byte >> 4) & 0x0F;
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/* isolate lower nibble */
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ns10 = (spd_byte & 0x0F);
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return (ns * 100 + ns10 * 10);
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}
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/*
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* translate ns coding of SPD timing values
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* into 10 ps unit values
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*/
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static inline unsigned short NSto10PS (unsigned char spd_byte)
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{
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return (spd_byte * 100);
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}
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#ifdef CONFIG_ZUMA_V2
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static int check_dimm (uchar slot, sdram_info_t * info)
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{
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/* assume 2 dimms, 2 banks each 256M - we dont have an
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* dimm i2c so rely on the detection routines later */
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memset (info, 0, sizeof (*info));
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info->slot = slot;
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info->banks = 2; /* Detect later */
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info->registered = 0;
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info->drb_size = 32; /* 16 - 256MBit, 32 - 512MBit
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but doesn't matter, both do same
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thing in setup_sdram() */
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info->tpar = 3;
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info->tras_clocks = 5;
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info->burst_len = 4;
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#ifdef CONFIG_ECC
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info->ecc = 0; /* Detect later */
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#endif /* CONFIG_ECC */
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return 0;
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}
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#elif defined(CONFIG_P3G4)
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static int check_dimm (uchar slot, sdram_info_t * info)
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{
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memset (info, 0, sizeof (*info));
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if (slot)
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return 0;
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info->slot = slot;
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info->banks = 1;
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info->registered = 0;
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info->drb_size = 4;
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info->tpar = 3;
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info->tras_clocks = 6;
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info->burst_len = 4;
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#ifdef CONFIG_ECC
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info->ecc = 2;
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#endif
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return 0;
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}
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#else /* ! CONFIG_ZUMA_V2 && ! CONFIG_P3G4 */
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/* This code reads the SPD chip on the sdram and populates
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* the array which is passed in with the relevant information */
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static int check_dimm (uchar slot, sdram_info_t * info)
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{
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uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
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int ret;
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uchar rows, cols, sdram_banks, supp_cal, width, cal_val;
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ulong tmemclk;
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uchar trp_clocks, trcd_clocks;
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uchar data[128];
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get_clocks ();
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tmemclk = 1000000000 / (gd->bus_clk / 100); /* in 10 ps units */
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#ifdef CONFIG_EVB64260_750CX
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if (0 != slot) {
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printf ("check_dimm: The EVB-64260-750CX only has 1 DIMM,");
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printf (" called with slot=%d insetad!\n", slot);
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return 0;
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}
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#endif
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DP (puts ("before i2c read\n"));
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ret = i2c_read (addr, 0, 128, data, 0);
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DP (puts ("after i2c read\n"));
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/* zero all the values */
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memset (info, 0, sizeof (*info));
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if (ret) {
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DP (printf ("No DIMM in slot %d [err = %x]\n", slot, ret));
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return 0;
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}
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/* first, do some sanity checks */
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if (data[2] != 0x4) {
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printf ("Not SDRAM in slot %d\n", slot);
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return 0;
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}
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/* get various information */
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rows = data[3];
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cols = data[4];
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info->banks = data[5];
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sdram_banks = data[17];
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width = data[13] & 0x7f;
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DP (printf
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("sdram_banks: %d, banks: %d\n", sdram_banks, info->banks));
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/* check if the memory is registered */
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if (data[21] & (BIT1 | BIT4))
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info->registered = 1;
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#ifdef CONFIG_ECC
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/* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */
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info->ecc = (data[11] & 2) >> 1;
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#endif
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/* bit 1 is CL2, bit 2 is CL3 */
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supp_cal = (data[18] & 0x6) >> 1;
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/* compute the relevant clock values */
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trp_clocks = (NSto10PS (data[27]) + (tmemclk - 1)) / tmemclk;
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trcd_clocks = (NSto10PS (data[29]) + (tmemclk - 1)) / tmemclk;
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info->tras_clocks = (NSto10PS (data[30]) + (tmemclk - 1)) / tmemclk;
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DP (printf ("trp = %d\ntrcd_clocks = %d\ntras_clocks = %d\n",
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trp_clocks, trcd_clocks, info->tras_clocks));
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/* try a CAS latency of 3 first... */
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cal_val = 0;
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if (supp_cal & 3) {
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if (NS10to10PS (data[9]) <= tmemclk)
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cal_val = 3;
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}
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/* then 2... */
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if (supp_cal & 2) {
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if (NS10to10PS (data[23]) <= tmemclk)
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cal_val = 2;
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}
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DP (printf ("cal_val = %d\n", cal_val));
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/* bummer, did't work... */
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if (cal_val == 0) {
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DP (printf ("Couldn't find a good CAS latency\n"));
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return 0;
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}
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/* get the largest delay -- these values need to all be the same
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* see Res#6 */
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info->tpar = cal_val;
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if (trp_clocks > info->tpar)
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info->tpar = trp_clocks;
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if (trcd_clocks > info->tpar)
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info->tpar = trcd_clocks;
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DP (printf ("tpar set to: %d\n", info->tpar));
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#ifdef CFG_BROKEN_CL2
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if (info->tpar == 2) {
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info->tpar = 3;
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DP (printf ("tpar fixed-up to: %d\n", info->tpar));
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}
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#endif
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/* compute the module DRB size */
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info->drb_size =
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(((1 << (rows + cols)) * sdram_banks) * width) / _16M;
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DP (printf ("drb_size set to: %d\n", info->drb_size));
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/* find the burst len */
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info->burst_len = data[16] & 0xf;
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if ((info->burst_len & 8) == 8) {
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info->burst_len = 1;
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} else if ((info->burst_len & 4) == 4) {
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info->burst_len = 0;
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} else {
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return 0;
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}
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info->slot = slot;
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return 0;
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}
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#endif /* ! CONFIG_ZUMA_V2 */
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static int setup_sdram_common (sdram_info_t info[2])
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{
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ulong tmp;
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int tpar = 2, tras_clocks = 5, registered = 1, ecc = 2;
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if (!info[0].banks && !info[1].banks)
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return 0;
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if (info[0].banks) {
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if (info[0].tpar > tpar)
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tpar = info[0].tpar;
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if (info[0].tras_clocks > tras_clocks)
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tras_clocks = info[0].tras_clocks;
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if (!info[0].registered)
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registered = 0;
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if (info[0].ecc != 2)
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ecc = 0;
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}
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if (info[1].banks) {
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if (info[1].tpar > tpar)
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tpar = info[1].tpar;
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if (info[1].tras_clocks > tras_clocks)
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tras_clocks = info[1].tras_clocks;
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if (!info[1].registered)
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registered = 0;
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if (info[1].ecc != 2)
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ecc = 0;
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}
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/* SDRAM configuration */
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tmp = GTREGREAD (SDRAM_CONFIGURATION);
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/* Turn on physical interleave if both DIMMs
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* have even numbers of banks. */
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if ((info[0].banks == 0 || info[0].banks == 2) &&
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(info[1].banks == 0 || info[1].banks == 2)) {
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/* physical interleave on */
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tmp &= ~(1 << 15);
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} else {
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/* physical interleave off */
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tmp |= (1 << 15);
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}
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tmp |= (registered << 17);
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/* Use buffer 1 to return read data to the CPU
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* See Res #12 */
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tmp |= (1 << 26);
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GT_REG_WRITE (SDRAM_CONFIGURATION, tmp);
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DP (printf ("SDRAM config: %08x\n", GTREGREAD (SDRAM_CONFIGURATION)));
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/* SDRAM timing */
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tmp = (((tpar == 3) ? 2 : 1) |
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(((tpar == 3) ? 2 : 1) << 2) |
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(((tpar == 3) ? 2 : 1) << 4) | (tras_clocks << 8));
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#ifdef CONFIG_ECC
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/* Setup ECC */
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if (ecc == 2)
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tmp |= 1 << 13;
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#endif /* CONFIG_ECC */
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GT_REG_WRITE (SDRAM_TIMING, tmp);
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DP (printf ("SDRAM timing: %08x (%d,%d,%d,%d)\n",
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GTREGREAD (SDRAM_TIMING), tpar, tpar, tpar, tras_clocks));
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/* SDRAM address decode register */
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/* program this with the default value */
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GT_REG_WRITE (SDRAM_ADDRESS_DECODE, 0x2);
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DP (printf ("SDRAM decode: %08x\n",
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GTREGREAD (SDRAM_ADDRESS_DECODE)));
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return 0;
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}
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/* sets up the GT properly with information passed in */
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static int setup_sdram (sdram_info_t * info)
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{
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ulong tmp, check;
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ulong *addr = 0;
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int i;
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/* sanity checking */
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if (!info->banks)
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return 0;
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/* ---------------------------- */
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/* Program the GT with the discovered data */
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/* bank parameters */
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tmp = (0xf << 16); /* leave all virt bank pages open */
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DP (printf ("drb_size: %d\n", info->drb_size));
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switch (info->drb_size) {
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case 1:
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tmp |= (1 << 14);
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break;
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case 4:
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case 8:
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tmp |= (2 << 14);
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break;
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case 16:
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case 32:
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tmp |= (3 << 14);
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break;
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default:
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printf ("Error in dram size calculation\n");
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return 1;
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}
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/* SDRAM bank parameters */
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/* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
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GT_REG_WRITE (SDRAM_BANK0PARAMETERS + (info->slot * 0x8), tmp);
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GT_REG_WRITE (SDRAM_BANK1PARAMETERS + (info->slot * 0x8), tmp);
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DP (printf
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("SDRAM bankparam slot %d (bank %d+%d): %08lx\n", info->slot,
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info->slot * 2, (info->slot * 2) + 1, tmp));
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/* set the SDRAM configuration for each bank */
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for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) {
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DP (printf ("*** Running a MRS cycle for bank %d ***\n", i));
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/* map the bank */
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memory_map_bank (i, 0, GB / 4);
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/* set SDRAM mode */
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GT_REG_WRITE (SDRAM_OPERATION_MODE, 0x3);
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check = GTREGREAD (SDRAM_OPERATION_MODE);
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/* dummy write */
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*addr = 0;
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/* wait for the command to complete */
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while ((GTREGREAD (SDRAM_OPERATION_MODE) & (1 << 31)) == 0);
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/* switch back to normal operation mode */
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GT_REG_WRITE (SDRAM_OPERATION_MODE, 0);
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check = GTREGREAD (SDRAM_OPERATION_MODE);
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/* unmap the bank */
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memory_map_bank (i, 0, 0);
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DP (printf ("*** MRS cycle for bank %d done ***\n", i));
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}
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return 0;
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}
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int dram_size (long int *base, long int maxsize)
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{
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volatile long int *addr, *b = base;
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long int cnt, val, save1, save2;
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#define STARTVAL (1<<20) /* start test at 1M */
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for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long);
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cnt <<= 1) {
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addr = base + cnt; /* pointer arith! */
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save1 = *addr; /* save contents of addr */
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save2 = *b; /* save contents of base */
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*addr = cnt; /* write cnt to addr */
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*b = 0; /* put null at base */
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/* check at base address */
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if ((*b) != 0) {
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*addr = save1; /* restore *addr */
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*b = save2; /* restore *b */
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return (0);
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}
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val = *addr; /* read *addr */
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*addr = save1;
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*b = save2;
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if (val != cnt) {
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/* fix boundary condition.. STARTVAL means zero */
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if (cnt == STARTVAL / sizeof (long))
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cnt = 0;
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return (cnt * sizeof (long));
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}
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}
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return maxsize;
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}
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|
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/* ------------------------------------------------------------------------- */
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|
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/* U-Boot interface function to SDRAM init - this is where all the
|
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* controlling logic happens */
|
|
long int initdram (int board_type)
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|
{
|
|
ulong checkbank[4] = {[0 ... 3] = 0 };
|
|
int bank_no;
|
|
ulong total;
|
|
int nhr;
|
|
sdram_info_t dimm_info[2];
|
|
|
|
|
|
/* first, use the SPD to get info about the SDRAM */
|
|
|
|
/* check the NHR bit and skip mem init if it's already done */
|
|
nhr = get_hid0 () & (1 << 16);
|
|
|
|
if (nhr) {
|
|
printf ("Skipping SDRAM setup due to NHR bit being set\n");
|
|
} else {
|
|
/* DIMM0 */
|
|
check_dimm (0, &dimm_info[0]);
|
|
|
|
/* DIMM1 */
|
|
#ifndef CONFIG_EVB64260_750CX /* EVB64260_750CX has only 1 DIMM */
|
|
check_dimm (1, &dimm_info[1]);
|
|
#else /* CONFIG_EVB64260_750CX */
|
|
memset (&dimm_info[1], 0, sizeof (sdram_info_t));
|
|
#endif
|
|
|
|
/* unmap all banks */
|
|
memory_map_bank (0, 0, 0);
|
|
memory_map_bank (1, 0, 0);
|
|
memory_map_bank (2, 0, 0);
|
|
memory_map_bank (3, 0, 0);
|
|
|
|
/* Now, program the GT with the correct values */
|
|
if (setup_sdram_common (dimm_info)) {
|
|
printf ("Setup common failed.\n");
|
|
}
|
|
|
|
if (setup_sdram (&dimm_info[0])) {
|
|
printf ("Setup for DIMM1 failed.\n");
|
|
}
|
|
|
|
if (setup_sdram (&dimm_info[1])) {
|
|
printf ("Setup for DIMM2 failed.\n");
|
|
}
|
|
|
|
/* set the NHR bit */
|
|
set_hid0 (get_hid0 () | (1 << 16));
|
|
}
|
|
/* next, size the SDRAM banks */
|
|
|
|
total = 0;
|
|
if (dimm_info[0].banks > 0)
|
|
checkbank[0] = 1;
|
|
if (dimm_info[0].banks > 1)
|
|
checkbank[1] = 1;
|
|
if (dimm_info[0].banks > 2)
|
|
printf ("Error, SPD claims DIMM1 has >2 banks\n");
|
|
|
|
if (dimm_info[1].banks > 0)
|
|
checkbank[2] = 1;
|
|
if (dimm_info[1].banks > 1)
|
|
checkbank[3] = 1;
|
|
if (dimm_info[1].banks > 2)
|
|
printf ("Error, SPD claims DIMM2 has >2 banks\n");
|
|
|
|
/* Generic dram sizer: works even if we don't have i2c DIMMs,
|
|
* as long as the timing settings are more or less correct */
|
|
|
|
/*
|
|
* pass 1: size all the banks, using first bat (0-256M)
|
|
* limitation: we only support 256M per bank due to
|
|
* us only having 1 BAT for all DRAM
|
|
*/
|
|
for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
|
|
/* skip over banks that are not populated */
|
|
if (!checkbank[bank_no])
|
|
continue;
|
|
|
|
DP (printf ("checking bank %d\n", bank_no));
|
|
|
|
memory_map_bank (bank_no, 0, GB / 4);
|
|
checkbank[bank_no] = dram_size (NULL, GB / 4);
|
|
memory_map_bank (bank_no, 0, 0);
|
|
|
|
DP (printf ("bank %d %08lx\n", bank_no, checkbank[bank_no]));
|
|
}
|
|
|
|
/*
|
|
* pass 2: contiguously map each bank into physical address
|
|
* space.
|
|
*/
|
|
dimm_info[0].banks = dimm_info[1].banks = 0;
|
|
for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
|
|
if (!checkbank[bank_no])
|
|
continue;
|
|
|
|
dimm_info[bank_no / 2].banks++;
|
|
dimm_info[bank_no / 2].size += checkbank[bank_no];
|
|
|
|
memory_map_bank (bank_no, total, checkbank[bank_no]);
|
|
#ifdef MAP_PCI
|
|
memory_map_bank_pci (bank_no, total, checkbank[bank_no]);
|
|
#endif
|
|
total += checkbank[bank_no];
|
|
}
|
|
|
|
#ifdef CONFIG_ECC
|
|
#ifdef CONFIG_ZUMA_V2
|
|
/*
|
|
* We always enable ECC when bank 2 and 3 are unpopulated
|
|
* If we 2 or 3 are populated, we CAN'T support ECC.
|
|
* (Zuma boards only support ECC in banks 0 and 1; assume that
|
|
* in that configuration, ECC chips are mounted, even for stacked
|
|
* chips)
|
|
*/
|
|
if (checkbank[2] == 0 && checkbank[3] == 0) {
|
|
dimm_info[0].ecc = 2;
|
|
GT_REG_WRITE (SDRAM_TIMING,
|
|
GTREGREAD (SDRAM_TIMING) | (1 << 13));
|
|
/* TODO: do we have to run MRS cycles again? */
|
|
}
|
|
#endif /* CONFIG_ZUMA_V2 */
|
|
|
|
if (GTREGREAD (SDRAM_TIMING) & (1 << 13)) {
|
|
puts ("[ECC] ");
|
|
}
|
|
#endif /* CONFIG_ECC */
|
|
|
|
#ifdef DEBUG
|
|
dump_dimm_info (&dimm_info[0]);
|
|
dump_dimm_info (&dimm_info[1]);
|
|
#endif
|
|
/* TODO: return at MOST 256M? */
|
|
/* return total > GB/4 ? GB/4 : total; */
|
|
return total;
|
|
}
|