Mark Kettenis f34e7fc29b sunxi: video: HDMI: Fix LCD clock divider ... Currently we may end up with an LCD clock divider that differs from the HDMI PHY clock divider if we can't exactly match the pixel clock. Fix this by using DIV_ROUND_UP to calculate the divider. This works since the PLL is chosen such that the resulting pixel clock is never higher than the requested pixel clock. Fixes: 1feed358ed ("sunxi: video: HDMI: Fix clock setup") Signed-off-by: Mark Kettenis <kettenis@openbsd.org>		2019-09-21 10:52:57 +02:00
..
lcdc.c	sunxi: use 6MHz PLL_VIDEO step for DE2 for higher resolution LCD	2018-11-13 22:17:06 +05:30
Makefile
simplefb_common.c
simplefb_common.h
sunxi_de2.c
sunxi_display.c	sunxi: display: Implement fallback to ddc probe when hpd fails	2019-02-15 16:30:44 +01:00
sunxi_dw_hdmi.c	sunxi: video: HDMI: Fix LCD clock divider	2019-09-21 10:52:57 +02:00
sunxi_lcd.c
tve_common.c