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u-boot-brain/arch/arm/include/asm/arch-omap5
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Tom Rini fa2f81b06f TI: Rework SRAM definitions and maximums 
On all TI platforms the ROM defines a "downloaded image" area at or near
the start of SRAM which is followed by a reserved area.  As it is at
best bad form and at worst possibly harmful in corner cases to write in
this reserved area, we stop doing that by adding in the define
NON_SECURE_SRAM_IMG_END to say where the end of the downloaded image
area is and make SRAM_SCRATCH_SPACE_ADDR be one kilobyte before this.
At current we define the end of scratch space at 0x228 bytes past the
start of scratch space this this gives us a lot of room to grow.  As
these scratch uses are non-optional today, all targets are modified to
respect this boundary.

Tested on OMAP4 Pandaboard, OMAP3 Beagle xM

Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Nagendra T S <nagendra@mistralsolutions.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Lokesh Vutla <lokeshvutla@ti.com>
Cc: Felipe Balbi <balbi@ti.com>
Cc: Igor Grinberg <grinberg@compulab.co.il>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: Paul Kocialkowski <contact@paulk.fr>
Cc: Enric Balletbo i Serra <eballetbo@gmail.com>
Cc: Adam Ford <aford173@gmail.com>
Cc: Steve Sakoman <sakoman@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Thomas Weber <weber@corscience.de>
Cc: Hannes Schmelzer <oe5hpm@oevsv.at>
Cc: Thomas Chou <thomas@wytron.com.tw>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Heiko Schocher <hs@denx.de>
Cc: Samuel Egli <samuel.egli@siemens.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
Cc: Ben Whitten <ben.whitten@gmail.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Mugunthan V N <mugunthanvnm@ti.com>
Cc: "B, Ravi" <ravibabu@ti.com>
Cc: "Matwey V. Kornilov" <matwey.kornilov@gmail.com>
Cc: Ladislav Michl <ladis@linux-mips.org>
Cc: Ash Charles <ashcharles@gmail.com>
Cc: "Kipisz, Steven" <s-kipisz2@ti.com>
Cc: Daniel Allred <d-allred@ti.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Ladislav Michl <ladis@linux-mips.org>
2016-09-06 13:41:42 -04:00
..
clock.h ARM: DRA7: Add macros for voltage values for all OPPs 2016-06-02 21:42:17 -04:00
cpu.h ARM: omap5: add platform specific ethernet phy modes configurations 2016-05-24 11:42:02 -05:00
dra7xx_iodelay.h ARM: OMAP5/DRA7: Expose do_set_iodelay 2016-03-27 09:12:15 -04:00
ehci.h arm: omap5: echi: Add GPL-2.0+ SPDX-License-Identifier 2013-09-20 10:30:54 -04:00
gpio.h SPDX-License-Identifier: fixing some problematic GPL-2.0 files 2013-08-19 15:34:13 -04:00
hardware.h ARM: dra7xx_evm: Enable EDMA3 in SPL to support DMA on qspi 2015-08-17 23:29:15 +05:30
i2c.h omap5/dra7: i2c: correct register offset for sync register 2016-07-26 08:39:23 +02:00
mem.h board/ti/dra7xx: add support for parallel NOR 2014-08-25 10:48:12 -04:00
mmc_host_def.h omap: consolidate common mmc definitions 2013-03-08 16:41:12 -05:00
mux_dra7xx.h ARM: DRA7: Add support for manual mode configuration 2015-06-12 13:02:05 -04:00
mux_omap5.h Add GPL-2.0+ SPDX-License-Identifier to source files 2013-07-24 09:44:38 -04:00
omap.h TI: Rework SRAM definitions and maximums 2016-09-06 13:41:42 -04:00
sata.h ARM: O5/dra7xx: Add SATA boot support 2014-02-19 10:47:45 -05:00
spl.h omap: SPL boot devices cleanup and completion 2015-07-27 15:02:04 -04:00
sys_proto.h arm: omap: Introduce vcores_init function 2016-06-02 21:42:18 -04:00