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5e479ccdf1
Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
27 lines
602 B
Plaintext
27 lines
602 B
Plaintext
menu "i.MX8M DDR controllers"
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depends on ARCH_IMX8M
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config IMX8M_DRAM
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bool "imx8m dram"
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config IMX8M_LPDDR4
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bool "imx8m lpddr4"
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select IMX8M_DRAM
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help
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Select the i.MX8M LPDDR4 driver support on i.MX8M SOC.
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config IMX8M_DDR4
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bool "imx8m ddr4"
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select IMX8M_DRAM
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help
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Select the i.MX8M DDR4 driver support on i.MX8M SOC.
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config SAVED_DRAM_TIMING_BASE
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hex "Define the base address for saved dram timing"
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help
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after DRAM is trained, need to save the dram related timming
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info into memory for low power use. OCRAM_S is used for this
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purpose on i.MX8MM.
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default 0x180000
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endmenu
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