mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-15 07:36:15 +09:00
a8a8fc9cee
This patch adds zynq spi controller nodes in zynq-7000.dtsi. Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Jagan Teki <jteki@openedev.com>
28 lines
864 B
Plaintext
28 lines
864 B
Plaintext
Zynq SPI controller Device Tree Bindings
|
|
----------------------------------------
|
|
|
|
Required properties:
|
|
- compatible : Should be "xlnx,spi-zynq".
|
|
- reg : Physical base address and size of SPI registers map.
|
|
- status : Status will be disabled in dtsi and enabled in required dts.
|
|
- interrupt-parent : Must be core interrupt controller.
|
|
- interrupts : Property with a value describing the interrupt
|
|
number.
|
|
- clocks : Clock phandles (see clock bindings for details).
|
|
- clock-names : List of input clock names - "ref_clk", "pclk"
|
|
(See clock bindings for details).
|
|
|
|
Example:
|
|
|
|
spi@e0006000 {
|
|
compatible = "xlnx,zynq-spi";
|
|
reg = <0xe0006000 0x1000>;
|
|
status = "disabled";
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <0 26 4>;
|
|
clocks = <&clkc 25>, <&clkc 34>;
|
|
clock-names = "ref_clk", "pclk";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
} ;
|